10 Commits

Author	SHA1	Message	Date
mrg	f5804e1cbf	Flatten bitcell array for LVS symmetries.	2019-07-16 11:53:20 -07:00
mrg	0b13225913	Single banks working with new RBL	2019-07-11 14:47:27 -07:00
mrg	b841fd7ce3	Replica bitcell array with arbitrary RBLs working	2019-07-10 15:56:51 -07:00
mrg	5c4df2410e	Fix dummy row LVS issue	2019-06-14 15:06:04 -07:00
Matt Guthaus	d23aa9a1bd	Use local setup.tcl and flatten bitcell arrays.	2019-04-26 14:12:51 -07:00
Matt Guthaus	3ffcad0db8	Add port makeall for removing symmetry problems in netgen	2019-04-26 09:17:52 -07:00
Matt Guthaus	bfca51f734	Fix flatten work-around code to have new circuit names	2019-01-18 09:51:52 -08:00
Matt Guthaus	ab7a83b7a5	Remove old setup.tcl and edit one in tech dir	2018-10-20 15:20:15 -07:00
Matt Guthaus	c0ffa9cc7b	Clean up magic config file copying. Add warning for missing files.	2018-10-05 08:36:12 -07:00
Matt Guthaus	b3fa6b9d52	Make setup.tcl file a technology file	2018-10-05 08:30:25 -07:00