ac8a16ebdf
Fix permissions for unit tests to be run standalone.
2018-08-28 10:31:58 -07:00
0f8da1510e
Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines.
2018-08-18 15:27:07 -07:00
e4a94e8597
Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist.
2018-08-15 04:00:48 -07:00
8d97862f6e
altered precharge array and precharge unit tests to accommodate multiport
2018-08-15 00:55:23 -07:00
9ffba4b052
Add +x permissions on precharge and pbitcell tests
2018-08-13 09:57:10 -07:00
5666ee6635
altered precharge module to accomodate bitlines from pbitcell, and altered unit test to test both bitcell and pbitcell configurations
2018-08-05 19:46:05 -07:00
c6503dd771
Modify unit tests to reset options during init_openram so
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that they don't use old parameters after a failure.
2018-07-10 16:39:32 -07:00
d4cd8aff15
Change permissions of tests
2018-05-14 16:36:58 -07:00
f34c4eb7dc
Convert entire OpenRAM to use python3. Works with Python 3.6.
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Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
2018-05-14 16:15:45 -07:00
56770f558f
Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds.
2018-01-29 16:59:29 -08:00
7a172873a3
Update unit tests to load verify after config file. Start magic DRC.
2018-01-12 10:24:49 -08:00
abee235963
Rewrite the parameterized transistor and gate classes.
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Changes propagate through all designs.
All modules use instance and layout pins.
2017-12-12 15:04:01 -08:00
1085497476
Fail when using Magic/netgen for DRC/LVS. Remove arguments in running precharge test.
2017-12-12 13:06:01 -08:00
37edd7cac6
Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.
2017-11-14 16:24:26 -08:00
cf940fb15d
Development version of new pin data structure. Tests pass LVS/DRC except for bank level.
2017-08-23 15:02:15 -07:00
Matt Guthaus
Michael Timothy Grimes