20 Commits

Author	SHA1	Message	Date
Matt Guthaus	e17c69be3e	Clean up new code for add_modules, add_pins and netlist/layouts.	2018-08-28 10:24:09 -07:00
Matt Guthaus	8664f7a0b8	Converted all modules to not run create_layout when netlist_only ... mode is enabled.	2018-08-27 16:42:48 -07:00
Matt Guthaus	19d46f5954	Finalized separation of netlist/layout creation.	2018-08-27 14:18:32 -07:00
Michael Timothy Grimes	8c73a26daa	Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly.	2018-08-26 14:37:17 -07:00
Matt Guthaus	34736b7b3f	Remove carriage returns form python files	2018-08-07 09:44:01 -07:00
Michael Timothy Grimes	ecd4612167	altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions	2018-08-05 19:43:59 -07:00
Michael Timothy Grimes	7b315a3b69	updating inverter to write transistor spacings	2018-07-12 20:52:05 -07:00
Matt Guthaus	ac7aa4537c	Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell.	2018-06-29 11:49:02 -07:00
Michael Timothy Grimes	fea304eac1	corrected gate to contact spacing	2018-05-31 18:31:34 -07:00
Michael Timothy Grimes	e19a422696	simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations	2018-05-31 17:39:51 -07:00
Michael Timothy Grimes	17769f27c6	small changes to pbitcell	2018-05-22 14:51:42 -07:00
Michael Timothy Grimes	7af95e4723	adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports.	2018-05-10 09:38:02 -07:00
Michael Timothy Grimes	7d3f7eefac	syntax corrections to pbitcell and modifying transistor sizes	2018-04-26 14:03:03 -07:00
Michael Timothy Grimes	0cc077598e	Added member functions to bitcell.py and pbitcell.py for use in bitcell_array.py. bitcell_array now used only one function for every type of bitcell.	2018-03-15 12:02:38 -07:00
Michael Timothy Grimes	65735c08e2	fixed bitcell_array to work with different sized pbitcells, changed sizing in pbitcell to minimize space between inverters	2018-03-08 16:39:26 -08:00
Michael Timothy Grimes	820a8440c9	adding unit test for bitcell array using pbitcell	2018-03-06 16:36:11 -08:00
Michael Timothy Grimes	fc294cb282	Fixed cell height and width	2018-03-02 10:53:29 -08:00
Michael Timothy Grimes	d33dec4e9e	Separated add_globals function into add_ptx and add_globals	2018-03-02 10:49:26 -08:00
Michael Timothy Grimes	d6ef91786b	updating pbitcell with latest layout optimizations	2018-02-28 17:56:13 -08:00
Michael Timothy Grimes	d41abb3074	moved pbitcell to new folder for parametrically sized cells	2018-02-28 11:25:22 -08:00