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OpenRAM
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1528 Commits

Author SHA1 Message Date
Matt Guthaus fcc4a75295 Create VCG using nets as nodes rather than pins. 2018-09-11 13:28:28 -07:00
Matt Guthaus add0e3ad68 Add none option for verify wrapper with warning messages. 2018-09-11 10:17:24 -07:00
Hunter Nichols 91bbc556e8 Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports. 2018-09-10 22:06:50 -07:00
Hunter Nichols da6843af5b Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done. 2018-09-10 19:33:59 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Michael Timothy Grimes 38a1f35ff0 Correcting format of file (removing tabs) 2018-09-10 03:44:08 -07:00
Michael Timothy Grimes a7f03858e8 Adding 'multiport_check' option to OPTS. All of the unit tests that have multiport checks in them are now under this conditional. If you want to remove the multiport drc/lvs checks, you can set the option to False, and it will skip those portions. 2018-09-09 23:25:29 -07:00
Michael Timothy Grimes 5af56e5a3a Adding layout check for sram (1 bank) using pbitcell and 1RW port 2018-09-09 22:45:25 -07:00
Michael Timothy Grimes 0cdd3b99bf Generalized wl names using bitcell's list_all_wl_names function to accomodate multiport 2018-09-09 22:42:52 -07:00
Michael Timothy Grimes 586c72e4f7 Altering certain tests to include multiport checks. 2018-09-09 22:08:03 -07:00
Michael Timothy Grimes 27427d4192 Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary. 2018-09-09 22:06:29 -07:00
Michael Timothy Grimes 252ae1effa add trailing 0 to web 2018-09-09 15:16:53 -07:00
Michael Timothy Grimes 68c00d7467 Removing din and dout list names in exchange for a read index. Write ports will always be in order (they will not skip numbers. Read ports however will skip the numbers assigned to wirte ports so the index of the read ports must be tracked. 2018-09-09 14:14:26 -07:00
Michael Timothy Grimes 1429b9ab1a Commiting working version of multi-port that can generate a netlist on the sram level. Changes that will clean up the code are forthcoming. 2018-09-09 14:00:51 -07:00
Michael Timothy Grimes c91735b23b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-08 18:56:58 -07:00
Matt Guthaus 2d86492d91 Working on methodology of blockages, pins, and routing multiple pins. 2018-09-08 18:55:36 -07:00
Matt Guthaus 96c51f3464 Component shape functions. Find connected pins through overlaps. 2018-09-08 10:05:48 -07:00
Hunter Nichols 5cab786e21 Cleaned up analyze and some of its helper functions to be less cluttered. 2018-09-07 17:50:09 -07:00
Matt Guthaus 69261a0dc1 Routing and connecting rails with vias done. 
Refactored grid path class.
Added direction enum.
Does not route multi-track width wires in signal router.
 2018-09-07 14:46:58 -07:00
Hunter Nichols 83f6434476 Gave find_feasible_period a port input. 2018-09-07 00:53:11 -07:00
Hunter Nichols 8aaf1155d1 Fixed test 23_lib_sram_test. Fixed syntax in related golden lib files. 2018-09-06 22:51:34 -07:00
Hunter Nichols 0ff3b29b66 Fixed test 23_sram_prune test. Fixed syntax errors in golden lib files. 2018-09-06 22:06:23 -07:00
Michael Timothy Grimes 1a340c9c85 Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell. 2018-09-06 19:36:50 -07:00
Hunter Nichols bf34911f3f Test 21_ngspice now passing for scmos and freepdk45. 21_hspice has leakage power error (but it may be okay) 2018-09-06 18:40:21 -07:00
Hunter Nichols 1615de05e4 Fixed leakage power issue in test 21_hspice. Still requires more testing. 2018-09-06 18:26:08 -07:00
Michael Timothy Grimes 66a8a76fb0 Commiting changes to pbitcell that separate the routing into individual functions and rename. The bitlines and wordlines are also renamed. 2018-09-06 17:59:21 -07:00
Hunter Nichols a2bc82fe71 Fixed test 21_hspice. Leakage power is off. 2018-09-06 17:34:22 -07:00
Hunter Nichols dd22f9acd5 Fixed issues with analytical sram test. Changed syntax errors in golden lib file. 2018-09-06 17:01:10 -07:00
Matt Guthaus c2c17a33d2 Horizontal and vertical grid wires done. 2018-09-06 14:30:59 -07:00
Matt Guthaus cd987479b8 Updates to supply routing. 
Rename astar_grid to signal_grid to parallel supply routing.
Wave expansion for supply rails.
Pin addition for supply rails.
 2018-09-06 11:54:14 -07:00
Hunter Nichols f824d039c6 Merge branch 'dev' into multiport_characterization 2018-09-06 00:25:11 -07:00
Hunter Nichols 66c4782408 Fixed several syntax error regarding some multiport naming. Currently in debug mode. 2018-09-06 00:25:02 -07:00
Hunter Nichols ad235c02c6 Added debug code which skips characterization and goes straight to writing the lib. Fixed some syntax issues in the lib file. 2018-09-05 23:27:13 -07:00
Matt Guthaus 59956f1446 Update signal routing for new blockage and pins. 2018-09-05 16:01:11 -07:00
Matt Guthaus 7ead566154 Remove cell rename during DRC. Keep flatten. 2018-09-05 16:00:48 -07:00
Matt Guthaus ee05865919 Change SCMOS comment drawing to stipple for easier visibility 2018-09-05 13:43:45 -07:00
Matt Guthaus b1c63a6c62 Add inflate blockages and remove pins from blockages. 2018-09-05 11:06:17 -07:00
Matt Guthaus 93b24d8c85 Merge remote-tracking branch 'origin/dev' into supply_routing 2018-09-05 11:05:41 -07:00
Matt Guthaus ba651d53ae Change options in pbitcell test to be global again. 2018-09-05 10:59:41 -07:00
Matt Guthaus 2a27fbc98e Fix temp directory preservation option. 
Make labels in freepdk45 replica bitcell lower case.
 2018-09-05 10:02:12 -07:00
Matt Guthaus 0f87ba742f Add back LEF blockages. Remove "absolute" flags from GDS output 2018-09-05 09:28:43 -07:00
Matt Guthaus 8ffdcdf277 Fixed bit shift amount error. Removed rotate flag for Calibre. 2018-09-04 17:27:50 -07:00
Matt Guthaus 73e2bd2653 Removed solid display format for comments to allow grid/blockage visibility. 2018-09-04 16:43:59 -07:00
Matt Guthaus 5395f21be9 Remove unique id in contact that was used for debugging 2018-09-04 16:40:52 -07:00
Matt Guthaus 9d40cd4a03 Remove verbose print statement in add_power_pin 2018-09-04 16:39:13 -07:00
Matt Guthaus 378993ca22 Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
Matt Guthaus d721fae5b0 Change labels in replica cell for freepdk45 too 2018-09-04 14:33:14 -07:00
Matt Guthaus 763f1e8dee Finish renaming replica bitcell and bitline pin names. 2018-09-04 14:03:15 -07:00
Matt Guthaus 4fc9278b73 Convert bounding box layer for SCMOS to bb, gds layer 63. 2018-09-04 13:05:21 -07:00
Matt Guthaus 6963a1092f Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00