60 Commits

Author	SHA1	Message	Date
Michael Timothy Grimes	19ca0d6c2a	Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port	2018-08-18 16:51:21 -07:00
Matt Guthaus	8900edbe12	Finalize single bank clock routing.	2018-08-14 10:36:35 -07:00
Matt Guthaus	3420b1002c	Connect data and column DFF clocks in 1 bank.	2018-08-14 10:09:41 -07:00
Matt Guthaus	f7f318d72e	Remove tri_en signals from bank control logic.	2018-08-13 14:47:03 -07:00
Matt Guthaus	a9c0ec5549	Add LVS correspondence points to each bank type	2018-07-18 14:29:04 -07:00
Matt Guthaus	58896a6f8e	Fix control signal names on control_logic input	2018-07-18 13:41:44 -07:00
Matt Guthaus	0665d51249	Must connect clock at top level for now	2018-07-17 14:24:07 -07:00
Matt Guthaus	ac22b1145f	Convert bank to use create_bus routines. ... Modify control logic to have correct offset in SRAM.	2018-07-16 14:13:41 -07:00
Matt Guthaus	f3ae29fe0b	Getting single bank to work reliably. Removed tri_gate from bank ... for now. Will add it in multibank arrays only. Not needed for separate DIN and DOUT ports.	2018-07-13 14:45:46 -07:00
Matt Guthaus	e6b1fcb44c	Refactor banks to use inheritance with a top-level SRAM wrapper class.	2018-07-12 10:30:45 -07:00