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OpenRAM
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942 Commits 4 Branches 63 Tags 78 MiB
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788 Commits

Author SHA1 Message Date
Matt Guthaus a3f13d6eab Remove banks from test configs 2018-09-24 11:41:51 -07:00
Matt Guthaus 2df9b79b28 Remove scn3me lib files. Remove bank references. 2018-09-24 11:28:43 -07:00
Matt Guthaus a58b1906ad Convert unit tests to scn4m_subm 
Also, fixed isdiff for python3.
 2018-09-17 11:13:46 -07:00
Matt Guthaus e591176211 Change default to scn4m 2018-09-13 15:26:03 -07:00
Matt Guthaus 93ae7ebd00 Specify DRC,LVS,PEX tool for scn4m 2018-09-13 15:18:30 -07:00
Matt Guthaus 571dca5d5f Hard code flatten commands for the unique id precharge array 2018-09-13 15:15:41 -07:00
Matt Guthaus 4d328c5768 Fix hspice setuphold golden results 2018-09-13 14:41:15 -07:00
Matt Guthaus f4389bdd8f Add extra track spacings in some routes. 2018-09-13 14:12:24 -07:00
Matt Guthaus 63d0523228 Added scn4m_subm. 
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
 2018-09-13 12:53:35 -07:00
Matt Guthaus 3539887ee4 Updating ms_flop removal. 
Updated characterizer for dff.
Added new setup/hold results for dff instead of ms_flop.
Removed ms_flop references in sram-base.
Fixed syntax errors in SCN3ME tech file.
 2018-09-13 11:40:24 -07:00
Matt Guthaus 66cbe0966c Removed old ms_flop unit test 2018-09-13 11:15:33 -07:00
Matt Guthaus f8fc7c12b3 Remove ms_flop and replace with dff. Might break setup_hold tests. 2018-09-13 11:02:28 -07:00
Michael Timothy Grimes bfc855b8b1 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-11 17:33:17 -07:00
Hunter Nichols ac3cc5c79b Merge branch 'dev' into multiport_characterization 2018-09-11 16:01:51 -07:00
Matt Guthaus a3c2b4384a Improve comments. Simplify function interface for channel route. 2018-09-11 15:53:12 -07:00
Hunter Nichols 676b6764c7 Merge branch 'dev' into multiport_characterization 2018-09-11 15:40:17 -07:00
Matt Guthaus 3587f90e94 Fix copy pasta error in create vertical channel route 2018-09-11 14:47:55 -07:00
Matt Guthaus 5e34233479 Finish new VCG testing. 
Reversed VCG graph edge directions.
Channel tracks get added left to right or top down like
normal left edge algorithm examples.
 2018-09-11 14:24:13 -07:00
Matt Guthaus fcc4a75295 Create VCG using nets as nodes rather than pins. 2018-09-11 13:28:28 -07:00
Matt Guthaus add0e3ad68 Add none option for verify wrapper with warning messages. 2018-09-11 10:17:24 -07:00
Hunter Nichols 91bbc556e8 Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports. 2018-09-10 22:06:50 -07:00
Hunter Nichols da6843af5b Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done. 2018-09-10 19:33:59 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Michael Timothy Grimes 38a1f35ff0 Correcting format of file (removing tabs) 2018-09-10 03:44:08 -07:00
Michael Timothy Grimes a7f03858e8 Adding 'multiport_check' option to OPTS. All of the unit tests that have multiport checks in them are now under this conditional. If you want to remove the multiport drc/lvs checks, you can set the option to False, and it will skip those portions. 2018-09-09 23:25:29 -07:00
Michael Timothy Grimes 5af56e5a3a Adding layout check for sram (1 bank) using pbitcell and 1RW port 2018-09-09 22:45:25 -07:00
Michael Timothy Grimes 0cdd3b99bf Generalized wl names using bitcell's list_all_wl_names function to accomodate multiport 2018-09-09 22:42:52 -07:00
Michael Timothy Grimes 586c72e4f7 Altering certain tests to include multiport checks. 2018-09-09 22:08:03 -07:00
Michael Timothy Grimes 27427d4192 Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary. 2018-09-09 22:06:29 -07:00
Michael Timothy Grimes 252ae1effa add trailing 0 to web 2018-09-09 15:16:53 -07:00
Michael Timothy Grimes 68c00d7467 Removing din and dout list names in exchange for a read index. Write ports will always be in order (they will not skip numbers. Read ports however will skip the numbers assigned to wirte ports so the index of the read ports must be tracked. 2018-09-09 14:14:26 -07:00
Michael Timothy Grimes 1429b9ab1a Commiting working version of multi-port that can generate a netlist on the sram level. Changes that will clean up the code are forthcoming. 2018-09-09 14:00:51 -07:00
Michael Timothy Grimes c91735b23b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-08 18:56:58 -07:00
Hunter Nichols 5cab786e21 Cleaned up analyze and some of its helper functions to be less cluttered. 2018-09-07 17:50:09 -07:00
Hunter Nichols 83f6434476 Gave find_feasible_period a port input. 2018-09-07 00:53:11 -07:00
Hunter Nichols 8aaf1155d1 Fixed test 23_lib_sram_test. Fixed syntax in related golden lib files. 2018-09-06 22:51:34 -07:00
Hunter Nichols 0ff3b29b66 Fixed test 23_sram_prune test. Fixed syntax errors in golden lib files. 2018-09-06 22:06:23 -07:00
Michael Timothy Grimes 1a340c9c85 Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell. 2018-09-06 19:36:50 -07:00
Hunter Nichols bf34911f3f Test 21_ngspice now passing for scmos and freepdk45. 21_hspice has leakage power error (but it may be okay) 2018-09-06 18:40:21 -07:00
Hunter Nichols 1615de05e4 Fixed leakage power issue in test 21_hspice. Still requires more testing. 2018-09-06 18:26:08 -07:00
Michael Timothy Grimes 66a8a76fb0 Commiting changes to pbitcell that separate the routing into individual functions and rename. The bitlines and wordlines are also renamed. 2018-09-06 17:59:21 -07:00
Hunter Nichols a2bc82fe71 Fixed test 21_hspice. Leakage power is off. 2018-09-06 17:34:22 -07:00
Hunter Nichols dd22f9acd5 Fixed issues with analytical sram test. Changed syntax errors in golden lib file. 2018-09-06 17:01:10 -07:00
Hunter Nichols f824d039c6 Merge branch 'dev' into multiport_characterization 2018-09-06 00:25:11 -07:00
Hunter Nichols 66c4782408 Fixed several syntax error regarding some multiport naming. Currently in debug mode. 2018-09-06 00:25:02 -07:00
Hunter Nichols ad235c02c6 Added debug code which skips characterization and goes straight to writing the lib. Fixed some syntax issues in the lib file. 2018-09-05 23:27:13 -07:00
Matt Guthaus b1c63a6c62 Add inflate blockages and remove pins from blockages. 2018-09-05 11:06:17 -07:00
Matt Guthaus 93b24d8c85 Merge remote-tracking branch 'origin/dev' into supply_routing 2018-09-05 11:05:41 -07:00
Matt Guthaus ba651d53ae Change options in pbitcell test to be global again. 2018-09-05 10:59:41 -07:00
Matt Guthaus 2a27fbc98e Fix temp directory preservation option. 
Make labels in freepdk45 replica bitcell lower case.
 2018-09-05 10:02:12 -07:00