18 Commits

Author	SHA1	Message	Date
Matt Guthaus	a0bf5345f8	Mostly working for 1 bank.	2018-03-23 08:14:26 -07:00
Matt Guthaus	8d9b79dfd8	Add dff_buf for buffered flop arrays.	2018-03-04 16:13:10 -08:00
Matt Guthaus	9559421ca8	Connect dff array clk in rows and columns.	2018-02-14 16:46:26 -08:00
Matt Guthaus	2d87dcda46	dff array done except for clock net	2018-02-14 16:03:29 -08:00
Matt Guthaus	0804a1eceb	Add new DFF. Create DFF module. Start dff_array, not tested.	2018-02-14 15:16:28 -08:00
Matt Guthaus	6f8744712d	Add extra pwc to 6T SCMOS cell.	2018-02-05 14:44:15 -08:00
Matt Guthaus	512448f9e8	Fix pin names to lower case. Fix write driver DRC errors and LVS error.	2018-01-31 17:37:16 -08:00
Matt Guthaus	51a72e26c7	Fix via1 BL disconnect error.	2018-01-31 10:35:28 -08:00
Matt Guthaus	c63eb3be3b	Fixed bug with missing tri gate via.	2018-01-29 17:29:30 -08:00
Matt Guthaus	8fcc8a1674	Increase height slightlty to allow pnand3 to pass DRC.	2018-01-29 15:30:58 -08:00
Matt Guthaus	1dc7752429	Fix 6T and replica cell contact spacing issues with Magic DRC. ... DRC/LVS passing for all parameterized gates. Magic and GDS match for SCMOS rules again.	2018-01-26 12:39:00 -08:00
Matt Guthaus	fb0355ebaf	Duplicate gnd label on metal1 pin in tri gate.	2018-01-24 13:20:34 -08:00
Matt Guthaus	039f531243	Capitalize bitline labels in write driver	2018-01-24 13:15:14 -08:00
Matt Guthaus	d84242719b	Change pin names in trigate and write_driver.	2018-01-24 13:12:36 -08:00
Matt Guthaus	ac8eada0d8	Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments.	2018-01-24 13:02:55 -08:00
Matt Guthaus	2468f224d9	SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh.	2018-01-22 17:14:39 -08:00
Matt Guthaus	fb2ed1d46c	Add wells to fix DRC errors in SCMOS library cells.	2018-01-22 16:28:20 -08:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00