12 Commits

Author	SHA1	Message	Date
Matt Guthaus	30fc81a1f0	Update copyright year.	2021-01-22 11:23:28 -08:00
mrg	87419bd640	Fix bitcell and pbitcell with different cell names	2020-11-03 11:30:40 -08:00
mrg	da721a677d	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
mrg	5514996708	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
Matthew Guthaus	b3fb4e3183	Make unit test configs generic to tech_name	2019-11-17 00:44:31 +00:00
Matthew Guthaus	c4cf8134fe	Undo changes for config expansion. Change unit tests to use OPENRAM_HOME.	2019-11-15 18:47:59 +00:00
Matt Guthaus	764d4da1bd	Clean up config file organization. Improve gdsMill debug output.	2019-10-23 10:48:18 -07:00
mrg	12fa36317e	Cleanup unit test. Fix s_en control bug for r-only.	2019-07-16 13:51:31 -07:00
mrg	17d144b5b5	Clean up multiport test options to be consistent.	2019-07-12 10:39:55 -07:00
mrg	0b13225913	Single banks working with new RBL	2019-07-11 14:47:27 -07:00
mrg	b841fd7ce3	Replica bitcell array with arbitrary RBLs working	2019-07-10 15:56:51 -07:00
mrg	bc4a3ee2b7	New port_data module works in SCMOS	2019-07-03 13:17:12 -07:00