14 Commits

Author	SHA1	Message	Date
mrg	229a3b5b3d	By default uniquify instances based on macro name.	2022-03-11 18:01:45 -08:00
mrg	48e35588f4	Fix cheat on wordline driver name.	2021-11-22 11:33:27 -08:00
mrg	779d6ad2b2	Debugging klayout for SCMOS and FreePDK45.	2021-11-22 11:33:27 -08:00
mrg	0c3ee643ab	Remove add_mod and add module whenever calling add_inst.	2021-11-22 11:33:27 -08:00
mrg	b7362ba011	Do not run same well spacing for backwards compatibility. Add pbitcell cheat.	2021-11-22 11:33:27 -08:00
mrg	8f296810be	Fix cheat on wordline driver name.	2021-11-22 11:33:27 -08:00
mrg	5d33db0ee4	Add write driver to well connect list	2021-11-22 11:33:27 -08:00
mrg	2e846cb22f	Fix regexes for cells without well taps	2021-11-22 11:33:27 -08:00
mrg	acc9b2d223	Connect pwell and bulk when no tap	2021-11-22 11:33:27 -08:00
mrg	7d7ffe76e0	Debugging klayout for SCMOS and FreePDK45.	2021-11-22 11:33:27 -08:00
mrg	0a91bd01c8	Fix DRC and LVS scripts	2021-09-16 15:37:26 -07:00
mrg	f3d1c6edc3	klayout DRC/LVS working	2021-09-15 11:33:39 -07:00
mrg	554b3f4ca7	Initial klayout DRC/LVS options	2021-09-07 16:51:16 -07:00
mrg	c117238fa7	Initial klayout DRC/LVS options	2021-08-03 14:41:09 -07:00