14 Commits

Author	SHA1	Message	Date
Matt Guthaus	1fe767343e	Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.	2018-11-07 11:31:44 -08:00
Hunter Nichols	b00fc040a3	Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.	2018-11-01 12:29:49 -07:00
Hunter Nichols	98a00f985b	Changed the analytical delay model to accept multiport options. Little substance to the values generated.	2018-10-26 00:08:13 -07:00
Hunter Nichols	6efe0f56c2	Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.	2018-10-26 00:08:13 -07:00
Hunter Nichols	8e243258e4	Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell.	2018-10-26 00:08:12 -07:00
Hunter Nichols	a711a5823d	Merged dev and fix conflicts in geometry.py	2018-10-24 10:52:22 -07:00
Matt Guthaus	e90f9be6f5	Move replica bitcells to new bitcells subdir	2018-10-24 09:06:29 -07:00
Hunter Nichols	53cb4e7f5e	Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working.	2018-10-22 23:33:01 -07:00
Michael Timothy Grimes	1a0568f244	Updating comments and cleaning up code for pbitcell.	2018-10-21 19:10:04 -07:00
Matt Guthaus	7591f25a2e	Merge branch 'dev' into supply_routing	2018-10-20 14:29:19 -07:00
Matt Guthaus	4bf1e206e2	Merge branch 'dev' into supply_routing	2018-10-17 09:47:18 -07:00
Matt Guthaus	a094db9077	Merge branch 'multiport' into supply_routing	2018-10-11 09:56:38 -07:00
Matt Guthaus	a2b1d025ab	Merge multiport	2018-10-08 11:45:50 -07:00
Matt Guthaus	68b30d601e	Move bitcells to their own directory in preparation for custom multiport cells.	2018-10-05 08:09:09 -07:00