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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 01:48:33 +02:00
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8e243258e491269eddb9735687912162f93cb524
OpenRAM/compiler/bitcells
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Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell.
2018-10-26 00:08:12 -07:00
..
bitcell_1rw_1r.py
Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell.
2018-10-26 00:08:12 -07:00
bitcell.py
Merge branch 'multiport' into supply_routing
2018-10-11 09:56:38 -07:00
pbitcell.py
Updating comments and cleaning up code for pbitcell.
2018-10-21 19:10:04 -07:00
replica_bitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00
replica_pbitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00
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