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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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53cb4e7f5eb8a7874b8c9c26c683675a6366b09f
OpenRAM/compiler/bitcells
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Hunter Nichols 53cb4e7f5e Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working.
2018-10-22 23:33:01 -07:00
..
bitcell_1rw_1r.py
Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working.
2018-10-22 23:33:01 -07:00
bitcell.py
Merge branch 'multiport' into supply_routing
2018-10-11 09:56:38 -07:00
pbitcell.py
Updating comments and cleaning up code for pbitcell.
2018-10-21 19:10:04 -07:00
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