OpenRAM

Commit Graph

Author	SHA1	Message	Date
Matt Guthaus	a6c2e77bcf	Move precharge and column mux cells to pgate directory. Move gnd to M3 in column mux. Create column mux cell unit test.	2018-04-06 17:15:14 -07:00
Matt Guthaus	97c08bce95	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. Shift s_en buffers even with other cells.	2018-03-23 08:14:09 -07:00
Matt Guthaus	696433b1ec	Add bank_sel to bank_select module as input. Remove reference to control in sram. Add dff_buf_array to options. Added inverted DFF Add variable height pinvbuf	2018-03-23 08:13:39 -07:00
Matt Guthaus	bab92fcf38	Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.	2018-03-23 08:13:20 -07:00
Matt Guthaus	ed8eaed54f	Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.	2018-03-23 08:12:47 -07:00
Hunter Nichols	d0dcd9f34b	Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.	2018-03-01 23:34:15 -08:00
Hunter Nichols	93ad99b9e1	Changed variable names in analytical power function to be more clear.	2018-02-28 12:32:54 -08:00
Hunter Nichols	6a3f0843ff	Fixed accidental changes made to analytical delay.	2018-02-28 12:18:41 -08:00
Hunter Nichols	d0e6dc9ce7	First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.	2018-02-26 16:32:28 -08:00
Hunter Nichols	beb7dad9bc	Added corner paramters to power functions. This commit does not compile (sorry)	2018-02-22 00:15:55 -08:00
Hunter Nichols	d4a0f48d4f	Added power calculations for inverter. Still testing.	2018-02-21 19:51:21 -08:00
Hunter Nichols	8ea384a761	Fixed merging issues with power branch	2018-02-14 15:21:42 -08:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00

13 Commits