OpenRAM

Commit Graph

Author	SHA1	Message	Date
Matt Guthaus	e5618b88af	Don't add sense amp to write only port. Fix write_and None define.	2019-08-11 08:46:36 -07:00
Matt Guthaus	d36f14b408	New control logic, netlist only working	2019-08-07 17:14:33 -07:00
Matt Guthaus	ff64e7663e	Add p_en_bar to write ports as well	2019-08-01 12:21:43 -07:00
Matt Guthaus	52029d8e48	Fix incorrect port_data BL pin name.	2019-07-27 06:11:45 -07:00
Matt Guthaus	179efe4d04	Fix bitline names in merge error	2019-07-26 22:03:50 -07:00
Matt Guthaus	0c5cd2ced9	Merge branch 'dev' into rbl_revamp	2019-07-26 18:01:43 -07:00
Matt Guthaus	5452ed69e7	Always have a precharge.	2019-07-25 10:31:39 -07:00
jsowash	2b29e505e0	Reversed order of wmask bits in functional.py since python lists go left to right. Made # of en bits equal to num_masks.	2019-07-22 12:44:35 -07:00
jsowash	0a5461201a	Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used.	2019-07-19 14:58:37 -07:00
jsowash	45cb159d7f	Connected wmask in the spice netlist.	2019-07-19 13:17:55 -07:00
jsowash	082decba18	Temporarily made the functional tests write/read only all 0's or 1's	2019-07-18 15:26:38 -07:00
jsowash	720739a192	Skipping test 22_sram_wmask_func_test and changed a typo of write_driver to write_mask	2019-07-17 11:04:17 -07:00
jsowash	ea2f786dcf	Redefined write_size inrecompute_sizes() to take the new word_size()	2019-07-15 14:41:26 -07:00
mrg	e550d6ff10	Port name maps between bank and replica array working.	2019-07-15 11:29:29 -07:00
jsowash	dfa2b29b8f	Begin adding wmask netlist and spice tests.	2019-07-12 10:34:29 -07:00
mrg	0b13225913	Single banks working with new RBL	2019-07-11 14:47:27 -07:00
mrg	b841fd7ce3	Replica bitcell array with arbitrary RBLs working	2019-07-10 15:56:51 -07:00
mrg	c0f9cdbc12	Create port address module	2019-07-05 09:03:52 -07:00
mrg	dd62269e0b	Some cleanup	2019-07-05 08:18:58 -07:00
Matt Guthaus	0cb86b8ba2	Exclude new precharge in graph build	2019-07-03 14:46:20 -07:00
mrg	bc4a3ee2b7	New port_data module works in SCMOS	2019-07-03 13:17:12 -07:00
mrg	244604fb0d	Data port module working by itself.	2019-07-02 15:35:53 -07:00

22 Commits