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OpenRAM
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3,816 Commits 4 Branches 63 Tags 78 MiB
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3284 Commits

Author SHA1 Message Date
samuelkcrow 45df34c774 add tests 2022-04-21 13:06:13 -07:00
samuelkcrow 9ec87c4d52 disable lvs/drc in char and func scripts 2022-04-14 10:13:48 -07:00
samuelkcrow 06cd2620f5 force netlist only mode in memchar memfunc, rename char and func scripts, add description for func script 2022-04-14 10:04:07 -07:00
samuelkcrow 4514927a7b log sim result after func_sim 2022-03-09 09:43:00 -08:00
samuelkcrow 8bbe39f5d1 Merge branch 'char' of https://github.com/VLSIDA/PrivateRAM into char 2022-03-04 13:54:09 -08:00
samuelkcrow ef710eae7a reorder sram __init__() argument order for tests that rely on the order 2022-03-04 13:53:20 -08:00
samuelkcrow 043e93e75e call create() function from sram/__init__ 2022-03-04 13:47:09 -08:00
samuelkcrow b216552c3f clarify file location message for user 2022-03-04 13:47:09 -08:00
samuelkcrow a89cd4deee characterizer and functional simulator working from command line 2022-03-04 13:47:09 -08:00
samuelkcrow f9bec36da5 Adding characterizer executable 2022-03-04 13:47:09 -08:00
mrg 353ff7859c Initial work on separate delay and func simulation 2022-03-04 13:47:09 -08:00
samuelkcrow 1acc6be3ce call create() function from sram/__init__ 2022-03-02 16:38:39 -08:00
samuelkcrow 910980328c clarify file location message for user 2022-03-02 12:47:05 -08:00
samuelkcrow d47b5612d5 characterizer and functional simulator working from command line 2022-03-02 12:18:54 -08:00
samuelkcrow a87b2e9446 Adding characterizer executable 2022-03-01 15:12:03 -08:00
mrg dd2effd28d Initial work on separate delay and func simulation 2022-02-16 10:54:39 -08:00
Jesse Cirimelli-Low 1a0861539a Merge branch 'opc_fix' into dev 2022-02-15 14:38:20 -08:00
Jesse Cirimelli-Low a54eb90371 place decoder rail contacts at least m2 min spacing away 2022-02-15 14:37:07 -08:00
mrg a35ab45843 Conditionally set TEST_TECHS. Skip pand4 for sky130. 2022-02-10 11:30:20 -08:00
mrg c471823626 Run individual tests on all technologies by default 2022-02-10 11:18:52 -08:00
mrg 51097b2c8b Revert rm in makefile 2022-02-02 09:38:27 -08:00
mrg 39f1199b63 Always delete result subdir to prevent bad and ok simultaneously 2022-02-02 09:36:19 -08:00
mrg 8fdd4966a7 Initial update of new psdm/nsdm implants 2022-02-02 09:36:05 -08:00
mrg 2d2620d21a Remove dir from bad tests 2022-02-02 07:11:13 -08:00
mrg c75968401c Update for detailed skips. Added some sky130 skips. 2022-02-08 16:04:43 -08:00
mrg 16238af584 Print failing tests before exit 2022-02-08 13:07:37 -08:00
mrg 4d62cbd345 Move pdk paths to docker invocation 2022-02-08 12:05:39 -08:00
mrg b1e1763e14 Fix PDK path for freepdk45 and list FAILED tests explicitly at end. 2022-02-08 11:35:29 -08:00
mrg b641bc8eef Check proper subdir for bad files 2022-02-07 16:30:18 -08:00
mrg a3d3aa514b Add target for all technologies 2022-02-07 11:27:10 -08:00
mrg ee97d87bdf Fix total regress pass or fail check. 2022-02-06 12:36:22 -08:00
mrg 89688de3cf Remove outside of docker space 2022-02-06 09:48:30 -08:00
mrg 93c6565b66 Add total failure of tests 2022-02-06 09:13:36 -08:00
mrg 8653b88206 Remove working temp directories 2022-02-06 09:06:20 -08:00
mrg d716a1c361 Don't stop on fail, archive all results, create .bad file on fail. 2022-02-05 07:50:06 -08:00
mrg e45e2f77c9 Rework regression to use docker. 2022-02-04 17:43:48 -08:00
mrg 049751ae1f FreePDK45 running with klayout and Sky130 running with magic. 2022-02-03 10:19:28 -08:00
mrg 63a6168b35 Merge branch 'dev' into klayout 2022-02-01 11:57:56 -08:00
mrg 06d391b3e3 Keep files during runs in Makefile 2022-01-13 14:41:24 -08:00
mrg 47690e0076 Merge branch 'dev' into docker 2021-12-29 14:42:32 -08:00
Jesse Cirimelli-Low 9e85d17fbe merge rbc lvs fixes 2021-12-23 21:21:10 -08:00
Jesse Cirimelli-Low c24c37a15a Merge branch 'dev' into lvs 2021-12-22 15:46:09 -08:00
mrg 34dd46c918 Exceptions for sky130 spare columns tests 2021-12-17 10:30:43 -08:00
mrg 82a1a8d87f Add exception for sky130 klayout LVS device output 2021-12-17 10:28:12 -08:00
mrg e460eff014 Add per tool lvs directories 2021-12-17 10:21:34 -08:00
mrg 4fa084f272 Add 1rw decoder test 2021-12-17 10:18:20 -08:00
Jesse Cirimelli-Low 8879820af4 replica col lvs fix 2021-12-15 14:19:52 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg b94dd79125 Add labels to noconn in dummy bitcell for klayout lvs 2021-11-22 11:33:27 -08:00
mrg b7362ba011 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00