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Add 1rw decoder test

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This commit is contained in:
mrg
2021-12-17 10:18:20 -08:00
parent 94c14c602c
commit 4fa084f272
3 changed files with 31 additions and 3 deletions
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compiler/tests/04_and2_dec_test.py
+10 -1
View File
@@ -29,7 +29,16 @@ class and2_dec_test(openram_test):
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and2_dec gate")
debug.info(2, "Testing and2_dec 1rw/1r gate")
a = factory.create(module_type="and2_dec")
self.local_check(a)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and2_dec 1rw gate")
a = factory.create(module_type="and2_dec")
self.local_check(a)
compiler/tests/04_and3_dec_test.py
+11 -1
View File
@@ -15,6 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class and3_dec_test(openram_test):
def runTest(self):
@@ -28,7 +29,16 @@ class and3_dec_test(openram_test):
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and3_dec gate")
debug.info(2, "Testing and3_dec 1rw/1r gate")
a = factory.create(module_type="and3_dec")
self.local_check(a)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and3_dec 1rw gate")
a = factory.create(module_type="and3_dec")
self.local_check(a)
compiler/tests/04_and4_dec_test.py
+10 -1
View File
@@ -30,7 +30,16 @@ class and4_dec_test(openram_test):
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and4_dec gate")
debug.info(2, "Testing and4_dec 1rw/1r gate")
a = factory.create(module_type="and4_dec")
self.local_check(a)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and4_dec 1rw gate")
a = factory.create(module_type="and4_dec")
self.local_check(a)