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merge rbc lvs fixes

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This commit is contained in:
Jesse Cirimelli-Low
2021-12-23 21:21:10 -08:00
parent 79e6eea976 cf8c486cea
commit 9e85d17fbe
8 changed files with 138 additions and 34 deletions
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compiler/modules/bitcell_base_array.py
+2 -2
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@@ -43,11 +43,11 @@ class bitcell_base_array(design.design):
# Make a flat list too
self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
def create_all_wordline_names(self, row_size=None):
def create_all_wordline_names(self, row_size=None, start_row=0):
if row_size == None:
row_size = self.row_size
for row in range(row_size):
for row in range(start_row, row_size):
for port in self.all_ports:
self.wordline_names[port].append("wl_{0}_{1}".format(port, row))