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OpenRAM
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24 Commits

Author SHA1 Message Date
Matt Guthaus 0c3baa5172 Added some comments to the spice files. 2019-01-25 15:00:00 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus b912f289a6 Remove extra X in instance names 2018-11-27 12:02:53 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Matt Guthaus a094db9077 Merge branch 'multiport' into supply_routing 2018-10-11 09:56:38 -07:00
Matt Guthaus e22e658090 Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
Matt Guthaus bb83e5f1be Move clk up in dff arrays for supply pin access 2018-10-05 08:18:38 -07:00
Matt Guthaus e17c69be3e Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
Matt Guthaus 6401cbf2a6 Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00
Matt Guthaus 138a70fc23 Add place_inst routine. 
Separate create netlist and layout in some modules.
 2018-08-27 10:42:40 -07:00
Matt Guthaus 3420b1002c Connect data and column DFF clocks in 1 bank. 2018-08-14 10:09:41 -07:00
Matt Guthaus a4bfbe3545 Move dff_array pins to center of rail 2018-07-25 15:08:04 -07:00
Matt Guthaus f43d4cc98f Fix routing clk connections of dff arrays 2018-07-18 11:38:58 -07:00
Matt Guthaus ef60b02a81 Add vdd/gnd pins to dff_array 2018-07-17 15:01:31 -07:00
Matt Guthaus f3ae29fe0b Getting single bank to work reliably. Removed tri_gate from bank 
for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
 2018-07-13 14:45:46 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Matt Guthaus c020d74f26 Add dff_buf and dff_array modules. 2018-03-23 08:11:51 -07:00
Matt Guthaus a2514878c1 Simplify dff array names of 1-dimension. Add ports on metal2. 2018-03-05 16:22:35 -08:00
Matt Guthaus 54f245cb9f Fix capitalization of pins in dff_array 2018-03-05 14:04:34 -08:00
Matt Guthaus 9559421ca8 Connect dff array clk in rows and columns. 2018-02-14 16:46:26 -08:00
Matt Guthaus 2d87dcda46 dff array done except for clock net 2018-02-14 16:03:29 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00