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luke/OpenRAM
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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
661 Commits 5 Branches 63 Tags
2e5d60ae87c02dd5ae9cfa671fb8f9220dcd4e41
Commit Graph
10 Commits
Author SHA1 Message Date
mguthaus cc99025279 Add log files for IP memories. 2018-02-25 11:25:20 -08:00
mguthaus f7a3fb90f0 Add SCMOS IP files. 2018-02-25 11:20:50 -08:00
mguthaus 44d85ecb94 First set of IP library components. Some DRC/LVS errors exist. Some timing characterization errors exist. Logs included with errors. 2018-02-25 11:16:01 -08:00
mguthaus 132c91d68f Adjust makefiles to continue on error. Turned on DRC/LVS to check for errors. 2018-02-23 15:46:13 -08:00
mguthaus a164a14b3f Add a bunch of config files 2018-02-23 15:27:18 -08:00
Matt Guthaus e51c4e8028 Increase verbosity in lib tests. 2018-02-23 07:48:12 -08:00
Matt Guthaus 4dc1f57881 Makefiles don't run DRC/LVS for now. 2018-02-22 11:14:36 -08:00
mguthaus b8b2375346 Updated golden tests with new leakage aware power numbers. 2018-02-21 15:44:52 -08:00
Matt Guthaus ea772b36d9 Unthread makefiles by default. Option to not DRC/LVS check lib for now. 2018-02-21 15:19:19 -08:00
mguthaus 2245ecffa0 Add SCMOS library file generation. 2018-02-12 13:18:14 -08:00
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