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OpenRAM
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3,979 Commits 4 Branches 63 Tags 78 MiB
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3383 Commits

Author SHA1 Message Date
Bugra Onal 219b29a833 Fake SRAM and Xyce RAW file option 2022-08-10 12:22:47 -07:00
samuelkcrow 8872a3e312 add tests 2022-08-10 12:22:47 -07:00
samuelkcrow 8d1d3c0e90 disable lvs/drc in char and func scripts 2022-08-10 12:22:47 -07:00
samuelkcrow e621890f78 force netlist only mode in memchar memfunc, rename char and func scripts, add description for func script 2022-08-10 12:22:47 -07:00
samuelkcrow 3e528a3e75 log sim result after func_sim 2022-08-10 12:22:47 -07:00
mrg 2adab1ea1a Initial work on separate delay and func simulation 2022-08-10 12:14:47 -07:00
samuelkcrow ebe4393d66 reorder sram __init__() argument order for tests that rely on the order 2022-08-10 12:07:09 -07:00
samuelkcrow 34ee709c69 call create() function from sram/__init__ 2022-08-10 12:07:07 -07:00
samuelkcrow 2bbd293bf2 clarify file location message for user 2022-08-10 12:06:18 -07:00
samuelkcrow 8793dda40a characterizer and functional simulator working from command line 2022-08-10 12:06:18 -07:00
samuelkcrow e2a52ec0f3 Adding characterizer executable 2022-08-10 12:06:18 -07:00
mrg 28128157c0 Initial work on separate delay and func simulation 2022-08-10 12:06:14 -07:00
samuelkcrow 1177df6193 move most of place_instances to base 2022-08-01 10:33:48 -07:00
samuelkcrow 1c8aeaa68a fix imports 2022-07-27 11:09:10 -07:00
samuelkcrow 2ff9ea4f78 move generic functions from control_logic module to new control_logic_base module 2022-07-26 23:22:02 -07:00
mrg 5db470155e Fix print errors in code format unit test. 2022-07-26 12:20:15 -07:00
mrg 69d5731d67 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2022-07-22 13:47:19 -07:00
Eren Dogan 03422be48c Fix carriage return 2022-07-22 19:54:35 +03:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
Eren Dogan 2a778dca82 Add whitespace check to code format test 2022-07-22 18:22:40 +03:00
Eren Dogan 64c72ee19d Fix typo 2022-07-22 18:15:27 +03:00
Eren Dogan 449c68ccae Fix file setup in code format test 2022-07-22 18:11:14 +03:00
mrg 6707a93c3c Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45. 2022-07-20 10:27:30 -07:00
mrg 3b0533c9c7 v1.2.0 2022-07-17 19:55:05 -07:00
mrg ff7ceaf92d Fix syntax error for module scope in row/col caps. 2022-07-13 17:19:09 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg ac86ad0e8a Move pdk installation inside docker to use Magic from docker image. 2022-06-21 12:10:15 -07:00
mrg dc9ae6cd1a Increase column width in netgen LVS scripts 2022-06-16 10:30:58 -07:00
mrg cf03454ecf Don't add wdriver_sel_n pins which aren't used. 2022-06-10 09:18:40 -07:00
mrg e744ffd6ea Move mount to shared target in openram.mk 2022-06-09 06:44:23 -07:00
mrg d30f05a1ae Update power layer on li for sky130 2022-06-08 17:19:26 -07:00
mrg 9e3a28237f Update port data test for sky130 single port 2022-06-08 17:18:53 -07:00
mrg 00ca2d45b6 Extract unique is option not command. 2022-06-08 15:06:06 -07:00
mrg 4814cf6eac Merge branch 'sky130_fixes' into dev 2022-06-08 14:27:30 -07:00
mrg 280582d4d6 Add missing via in dff array 2022-06-08 14:24:17 -07:00
mrg 76bc4e1fc2 Only do one extract. Flatten transistors since bug fixed in magic. 2022-06-08 14:23:50 -07:00
mrg ad6633ddca Update versions of tools. Fix supply bug in predecode. 2022-06-08 13:50:25 -07:00
Jesse Cirimelli-Low fbe3032246 add case for single spare col spare_wen_dff i/o 2022-05-26 12:18:47 -07:00
mrg 1bab395946 Merge branch 'sky130_fixes' into dev 2022-05-24 09:12:37 -07:00
mrg cb3d7b9d5d Add spares for sky130 unit tests. 2022-05-23 17:27:26 -07:00
mrg b84b4dab43 Fail on pin mismatch too. 2022-05-23 16:28:28 -07:00
mrg 8c85230033 Remove experimental power option. 2022-05-23 10:08:35 -07:00
mrg 51b0f125fb Add offset to 0,0 that was inadvertantly removed for router debug. 2022-05-23 09:59:41 -07:00
mrg 735d66c9f1 Start dff array supplies on first rather than second bit. 2022-05-17 15:54:54 -07:00
mrg 3e02a0e7df Update column decoder and dff array supplies 2022-05-17 15:49:50 -07:00
mrg c8905c410a Fix case where distance is zero length comparison 2022-05-17 15:49:06 -07:00
mrg f1f4453d14 Add column decoder module with power supply straps. 2022-05-17 13:32:19 -07:00
mrg 8217a84165 Uniquify overlap points during segment overlap computation. 2022-05-17 13:31:23 -07:00
mrg 9b592ab432 Fix missing hash recompute in vector class. 2022-05-17 13:30:41 -07:00
mrg bed12d2a9e pbitcell vdd/gnd are on layer m1 only. 2022-05-16 17:02:53 -07:00