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3,196 Commits 4 Branches 63 Tags 78 MiB
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66 Commits

Author SHA1 Message Date
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Hunter Nichols 8c1fe253d5 Added variable fanouts to delay testing. 2019-02-13 22:24:58 -08:00
Hunter Nichols 6d3884d60d Added corner data collection. 2019-01-22 16:40:46 -08:00
Hunter Nichols 51b1bd46da Added option to use delay chain size defined in tech.py 2018-12-14 18:02:19 -08:00
Hunter Nichols 97fc37aec1 Added checks for the bitline voltage at sense amp enable 50%. 2018-12-12 23:59:32 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 5d59863efc Fix p_en_bar at top level. Change default scn4m period to 10ns. 2018-11-27 14:44:55 -08:00
Hunter Nichols 8957c556db Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass. 2018-10-30 22:19:26 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Matt Guthaus f4389bdd8f Add extra track spacings in some routes. 2018-09-13 14:12:24 -07:00
Matt Guthaus 63d0523228 Added scn4m_subm. 
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
 2018-09-13 12:53:35 -07:00