 mrg
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febf7031b1
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Fix wrong power layer for min area constraint
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2022-03-02 17:04:54 -08:00 |
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mrg
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7654cd7295
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Allow supply pins on m4 too
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2022-03-02 16:47:17 -08:00 |
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 samuelkcrow
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1acc6be3ce
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call create() function from sram/__init__
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2022-03-02 16:38:39 -08:00 |
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mrg
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51ba88d896
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Port address with vertical power stripes
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2022-03-02 16:29:43 -08:00 |
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samuelkcrow
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910980328c
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clarify file location message for user
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2022-03-02 12:47:05 -08:00 |
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samuelkcrow
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d47b5612d5
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characterizer and functional simulator working from command line
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2022-03-02 12:18:54 -08:00 |
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samuelkcrow
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a87b2e9446
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Adding characterizer executable
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2022-03-01 15:12:03 -08:00 |
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mrg
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4fac069c3c
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Skip hspice tests in docker
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2022-03-01 14:44:04 -08:00 |
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mrg
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f7e3672c89
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Route horizontal supplies in write driver.
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2022-03-01 14:37:51 -08:00 |
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mrg
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36bbf81624
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Upgrade to magic 8.3.274
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2022-03-01 14:37:30 -08:00 |
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mrg
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0908aa9e25
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Add route vertical pins
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2022-03-01 14:37:09 -08:00 |
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mrg
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c12c006799
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Add verbose option
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2022-03-01 10:50:49 -08:00 |
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mrg
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38494458e3
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Fix incorrect port 1w to 1r
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2022-03-01 10:44:56 -08:00 |
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mrg
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c223c1ad1c
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Run docker pull before running all tests for regression
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2022-03-01 10:33:40 -08:00 |
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mrg
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184888b370
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Skip 16 way test for now
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2022-02-28 12:03:01 -08:00 |
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mrg
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27b4d2edb1
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Add 16 way mux SRAM tests
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2022-02-28 11:53:24 -08:00 |
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mrg
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54bd022efc
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Rework precharge route supply horizontally
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2022-02-28 11:36:10 -08:00 |
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mrg
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8b4ef9b6c1
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Upgrade to newest magic bug fixes
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2022-02-28 09:11:09 -08:00 |
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mrg
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2520d9f590
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Remove commented code in precharge array
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2022-02-25 16:21:12 -08:00 |
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mrg
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9b90a44d4a
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Move output in freepdk45 sense amp down to prevent router conflict with supply
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2022-02-25 16:20:47 -08:00 |
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mrg
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7b77378927
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Add layer to horizontal pin help and use in precharge
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2022-02-25 10:45:25 -08:00 |
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mrg
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12a6f1f2ee
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Add missing well tap
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2022-02-25 10:44:40 -08:00 |
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mrg
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82c2bc329f
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Split bank and col mux tests.
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2022-02-23 15:39:32 -08:00 |
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mrg
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5376b5bf20
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Fix offset to center select signal between bitlines
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2022-02-23 15:38:11 -08:00 |
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mrg
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6389d4ac82
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Skip all func tests
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2022-02-23 15:31:15 -08:00 |
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mrg
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baf369fc96
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Convert power to rails rather than pins in sense amp and precharge
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2022-02-23 14:06:49 -08:00 |
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mrg
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d4c14d7d19
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Add horizontal pin helper function
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2022-02-23 14:06:19 -08:00 |
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mrg
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5451a8d07a
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Don't make internal bus pins because magic will extract ports
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2022-02-23 14:06:01 -08:00 |
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mrg
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6a295aeb38
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Give feedback warnings in magic output
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2022-02-23 13:05:03 -08:00 |
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mrg
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744dfc5fa7
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Use older version of netgen
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2022-02-23 13:04:53 -08:00 |
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mrg
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1742927751
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Split port data tests into individual tests
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2022-02-23 11:12:32 -08:00 |
|
 Bugra Onal
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f971a83e68
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Base-verilog
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2022-02-23 10:34:48 -08:00 |
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mrg
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b71230efd7
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Update Magic and klayout versions in docker
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2022-02-23 10:20:18 -08:00 |
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mrg
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16d54e4fcb
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Use vlsida repo for sram library
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2022-02-23 10:19:46 -08:00 |
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mrg
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53e4c45038
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Add tap to nand in pnand
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2022-02-23 09:30:31 -08:00 |
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mrg
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abac5a11ab
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Move power supply stack to design
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2022-02-18 15:02:45 -08:00 |
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mrg
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80a4fc7e84
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Add PYTHONPATH in setup file
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2022-02-18 15:02:16 -08:00 |
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mrg
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dd2effd28d
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Initial work on separate delay and func simulation
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2022-02-16 10:54:39 -08:00 |
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Bugra Onal
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9c35add8d6
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Base template additions
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2022-02-16 10:53:18 -08:00 |
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mrg
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4590874ffa
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Merge branch 'dev' into sky130_fixes
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2022-02-16 09:31:49 -08:00 |
|
 Jesse Cirimelli-Low
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1a0861539a
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Merge branch 'opc_fix' into dev
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2022-02-15 14:38:20 -08:00 |
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Jesse Cirimelli-Low
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a54eb90371
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place decoder rail contacts at least m2 min spacing away
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2022-02-15 14:37:07 -08:00 |
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mrg
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bb24503f32
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Add back klayout lvs model install.
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2022-02-11 13:48:52 -08:00 |
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mrg
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abbdaeb60f
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Merge branch 'lvs' into sky130_fixes
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2022-02-11 13:24:27 -08:00 |
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mrg
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a75d9fcc76
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Fix failing test output of Makefile
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2022-02-11 13:11:24 -08:00 |
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mrg
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ab3acb99da
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Fix offsets of new nwell/pwell contacts.
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2022-02-11 12:09:42 -08:00 |
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mrg
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ed5765ea87
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Merge branch 'klayout' into dev
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2022-02-10 11:30:32 -08:00 |
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mrg
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a35ab45843
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Conditionally set TEST_TECHS. Skip pand4 for sky130.
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2022-02-10 11:30:20 -08:00 |
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mrg
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c471823626
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Run individual tests on all technologies by default
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2022-02-10 11:18:52 -08:00 |
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Bugra Onal
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6dc42a7bbb
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Verilog Template additions
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2022-02-07 11:23:43 -08:00 |
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