Emil J. Tywoniak
2dc8c1474f
tests: cover twines, name publicity, hashing and sorting
2026-10-02 18:42:01 +02:00
nella
a74edc9be8
Check shift B signedness in shiftadd.
2026-09-30 18:15:40 +02:00
nella
3b7c09934a
Materialize A sign extension in shiftadd.
...
$shr and $shift sign-extend A to max(A_WIDTH, Y_WIDTH) before shifting.
shiftadd resliced A without that extension and left A_SIGNED set, so the
narrowed A was sign-extended a second time, from the wrong bit. Bake the
extension in before reslicing and clear A_SIGNED.
When the constant offset consumed all of A this also left an empty A on a
signed $shr, which techmap lowered to x.
Fixes #6214 , fixes #6041 .
2026-09-23 08:00:44 +02:00
nella
57ab8ef2c6
Merge remote-tracking branch 'origin/main' into nella/latch-diagnostics-2
2026-09-22 16:49:41 +02:00
nella
0edda7a3ab
Merge pull request #6201 from YosysHQ/nella/check-internal-celltypes
...
check: reject unknown internal cell types [sc-915]
2026-09-15 11:52:15 +00:00
Lofty
d85872386a
Merge pull request #6174 from YosysHQ/lofty/abc-refactor-16
...
abc9: migrate to write_xaiger2
2026-09-14 16:25:07 +00:00
nella
76213a5d4c
Reject unknown internal cell types in check and hierarchy -check.
...
A $-prefixed cell type must be a known cell type or a module in the
design. check reports it as a problem, hierarchy -check errors.
2026-09-14 13:50:09 +02:00
Miodrag Milanovic
5cdba4fbd7
Update tests to reflect change to <inlined>
2026-09-14 10:35:11 +02:00
Emil J
370a53acf8
Merge pull request #6169 from YosysHQ/emil/check-process-conflicts
...
check: detect process-driver conflicts
2026-09-09 16:52:20 +00:00
Emil J. Tywoniak
d8a4bf0c82
check: detect process-driver conflicts
2026-09-02 15:28:01 +02:00
nick
3deb8f313e
fix 6151 - adding error cases to formal backends / also adding test
...
cases
2026-09-01 14:34:28 -06:00
nella
e741bd009f
Add shift, mul, eqx to aiger2.
2026-09-01 12:47:01 +01:00
John Kearney
0f5efca3c9
json: read 'signed' attribute on netnames, matching ports
...
The JSON backend writes "signed": 1 for any signed wire, including
internal nets. The frontend only parsed the attribute for ports,
so a write-read roundtrip silently cleared is_signed on internal
nets. Signed internal wires became unsigned between the two passes.
Fix: parse 'signed' in the netnames loop, next to the existing
upto/offset handling. Regression test does a full roundtrip and
checks the internal signed wire survives.
2026-08-20 22:20:24 -07:00
ZaneHam
b7b8ea9784
smt2, btor: error on $check cells instead of dropping them
...
Both backends only looked for $assert/$assume/$cover, so a $check cell was
never visited and the resulting formal output carried no proof obligations at
all. write_smv already errors via its catch-all; this follows its message.
2026-08-14 00:15:34 +12:00
nella
1dbe897ab3
Test.
2026-08-10 15:56:02 +02:00
Emil J
72ce1b63d7
Merge pull request #6090 from YosysHQ/emil/hierarchy-fix-keep-cache-again
...
hierarchy: fix keep cache usage by caching false too 2
2026-08-05 21:54:55 +00:00
Emil J. Tywoniak
253388a87f
hierarchy: fix cache usage by caching false too 2
2026-08-05 23:32:37 +02:00
Catherine
f26ef15b2a
Revert "hierarchy: regression test for keep cache"
...
This reverts commit a27378cff8
2026-08-05 16:52:59 +00:00
Miodrag Milanovic
ebf286ab40
Code cleanup
2026-08-04 17:18:22 +02:00
Emil J
468ba27d91
Merge pull request #6078 from YosysHQ/emil/hierarchy-fix-keep-cache
...
hierarchy: fix keep cache usage by caching false too
2026-08-03 15:54:50 +00:00
Emil J. Tywoniak
a27378cff8
hierarchy: regression test for keep cache
2026-08-03 17:36:49 +02:00
nella
abe32c86a0
Merge 'origin/main' into emil/muxpack-fix-chain.
2026-08-03 11:50:21 +02:00
nella
4baff94575
Add nesting test.
2026-07-31 10:31:44 +02:00
nella
250a467518
Attr file:line.
2026-07-31 10:31:44 +02:00
nella
2b5755178f
Clean up diagnostics.
2026-07-31 10:31:44 +02:00
Emil J. Tywoniak
8565451ef9
autoname: selection determines what gets renamed, not the name it gets renamed to
2026-07-17 22:48:46 +02:00
Emil J. Tywoniak
fb0bb160ad
autoname: rewrite
2026-07-17 12:02:43 +02:00
Lofty
75286287c6
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7
...
Move rename logic to abc_ops_reintegrate
2026-07-09 08:46:46 +00:00
nella
f5809a7c2c
Merge branch 'main' into nella/latch-toggle
2026-07-08 11:41:08 +02:00
nella
6675c45e29
Fix (async latch).
2026-06-24 13:01:52 +02:00
nella
a800a5b5cb
Fix.
2026-06-24 12:13:55 +02:00
nella
a8b4715298
Fix.
2026-06-24 11:48:20 +02:00
nella
1186e5af61
Fix.
2026-06-24 11:11:19 +02:00
nella
a3b8609c84
Add -nolatches check option.
2026-06-24 10:38:10 +02:00
Miodrag Milanovic
a689342207
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a
End of file fix
2026-06-23 07:23:41 +02:00
nella
8f5d2d5894
Use -assert-none.
2026-06-22 11:12:00 +02:00
Lofty
091d2a7814
Move rename logic to abc_ops_reintegrate
2026-06-19 10:46:47 +01:00
nella
b3b1394cf1
Fixup level policy.
2026-06-18 18:00:51 +02:00
nella
32a268d745
Emit errors before dfflegalize.
2026-06-18 17:07:24 +02:00
nella
b2d688dbf9
Error out on latches.
2026-06-17 17:36:32 +02:00
nella
c814ef35e3
Emit latch warning.
2026-06-17 11:27:43 +02:00
nella
a46bc77eeb
Fix nolatch test.
2026-06-15 15:27:58 +02:00
nella
01e2698247
Add latch check step.
2026-06-15 15:09:23 +02:00
nella
83a8245734
Add muxcover regression test.
2026-06-10 14:46:04 +02:00
Miodrag Milanovic and Catherine
ce280354cf
Update CI scripts for CMake
...
Co-authored-by: Catherine <[email protected]
2026-06-03 08:58:11 +00:00
Philippe Sauter
c89cfe1e6e
peepopt: add shiftpow2 pattern
...
Rewrite power-of-two indexed word selects to $bmux when the shift
amount already carries the scale as low zero bits.
Keep the rule to non-overlapping selections and bound the generated
mux ways. Add regressions for aligned shifts, padding, signed
extension, and shiftmul handoff cases.
2026-05-31 02:01:32 +02:00
junyao
6f111118de
proc: ignore nosync temporaries in always_latch checks
2026-05-26 00:56:07 +08:00
Miodrag Milanovic
c0779f488a
Make out of tree build testing possible
2026-05-19 14:26:07 +02:00
Emil J. Tywoniak
334dd7b80c
muxpack: reject slicing of predecessor Y ports in mux chain
2026-05-13 10:27:05 +02:00
Emil J. Tywoniak
nella
nella
Lofty
Miodrag Milanovic
Emil J
nick
John Kearney
ZaneHam
Catherine
Philippe Sauter
junyao