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1711 Commits

Author SHA1 Message Date
Akash Levy a43de44f9d Merge upstream changes 2025-09-10 23:02:15 -07:00
Robert O'Callahan d34ac0c87d Make `log()` use the `FmtString` infrastructure. 
Now `log()` supports `std::string`.

We have to fix a few places where the format parameter was not a compile time constant.
This is mostly trivial.
 2025-09-09 15:41:03 +02:00
Akash Levy 1b3375d8df Merge upstream in 2025-09-09 05:50:48 -07:00
Akash Levy 8204fd1d0b Update Yosys to latest 2025-09-06 16:49:39 -07:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Jannis Harder 41452e43b2
Merge pull request #4475 from georgerennie/skip_cover 
smtbmc: Support skipping steps in cover mode
 2025-09-01 13:53:04 +02:00
Jannis Harder 501bf4ce40
Merge pull request #4711 from georgerennie/george/btor_buf 
write_btor: support $buf
 2025-09-01 13:38:25 +02:00
Akash Levy e54fa487b8 Merge from upstream 2025-08-21 17:56:55 -07:00
Robert O'Callahan e0e70d1158 Remove some `c_str()` calls where they're no longer needed as parameters to `stringf()`. 2025-08-18 14:20:31 +01:00
Akash Levy 3733ad3879
Merge branch 'YosysHQ:main' into main 2025-08-11 09:26:32 -07:00
Hongce Zhang 76e507f307 update verilog_backend according to Github comments 2025-08-08 16:17:37 +08:00
Akash Levy 77be4d7be7 Bump Yosys to latest 2025-08-07 17:22:25 -07:00
Hongce Zhang b635ab72bf Merge branch 'main' of github.com:zhanghongce/yosys 2025-08-07 11:37:55 +08:00
Hongce Zhang 3cbbb9456d reorder verilog backend port wires 2025-08-07 11:37:23 +08:00
Krystine Sherwin 3959d19291
Reapply "Add groups to command reference" 
This reverts commit 81f87ce6ed.
 2025-08-06 13:52:12 +12:00
Akash Levy cc733fd11b Merge from upstream 2025-07-30 22:50:14 -07:00
Miodrag Milanović 1d229ae254
Merge pull request #5221 from rocallahan/typed-stringf 
Introduce variadic template implementation of `stringf` that supports `std::string` parameters
 2025-07-29 15:12:49 +02:00
Robert O'Callahan 6ee3cd8ffd Replace `stringf()` with a templated function which does compile-time format string checking. 
Checking only happens at compile time if -std=c++20 (or greater) is enabled. Otherwise
the checking happens at run time.

This requires the format string to be a compile-time constant (when compiling with
C++20), so fix a few places where that isn't true.

The format string behavior is a bit more lenient than C printf. For %d/%u
you can pass any integer type and it will be converted and output without
truncating bits, i.e. any length specifier is ignored and the conversion is
always treated as 'll'. Any truncation needs to be done by casting the argument itself.
For %f/%g you can pass anything that converts to double, including integers.

Performance results with clang 19 -O3 on Linux:
```
hyperfine './yosys -dp "read_rtlil /usr/local/google/home/rocallahan/Downloads/jpeg.synth.il; dump"'
```
C++17 before: Time (mean ± σ):     101.3 ms ±   0.8 ms    [User: 85.6 ms, System: 15.6 ms]
C++17 after:  Time (mean ± σ):      98.4 ms ±   1.2 ms    [User: 82.1 ms, System: 16.1 ms]
C++20 before: Time (mean ± σ):     100.9 ms ±   1.1 ms    [User: 87.0 ms, System: 13.8 ms]
C++20 after:  Time (mean ± σ):      97.8 ms ±   1.4 ms    [User: 83.1 ms, System: 14.7 ms]

The generated code is reasonably efficient. E.g. with clang 19, `stringf()` with a format
with no %% escapes and no other parameters (a weirdly common case) often compiles to a fully
inlined `std::string` construction. In general the format string parsing is often (not always)
compiled away.
 2025-07-29 05:29:33 +00:00
N. Engelhardt 81f87ce6ed
Revert "Add groups to command reference" 2025-07-23 14:41:49 +00:00
Robert O'Callahan f25f8fe7c4 In the Verilog backend, only sort modules that we're going to emit. 
If you have a large design with a lot of modules and you use the Verilog
backend to emit modules one at a time to separate files, performance is
very low. The problem is that the Verilog backend calls `design->sort()`
every time, which sorts the contents of all modules, and this is slow
even when everything is already sorted.

We can easily fix this by only sorting the contents of modules that
we're actually going to emit.
 2025-07-21 05:32:31 +00:00
Krystine Sherwin d62a110dc8
register.h: Add internal_flag to Pass 
Update experimental pass warnings to use a shared function.  Reduces repetition, and also allows all of the warning flags to be combined (which at present is just experimental and the new internal).
Update `test_*` passes to call `internal()` in their constructors.
 2025-07-21 10:35:19 +12:00
Akash Levy 37806d5ea7
Merge branch 'YosysHQ:main' into main 2025-07-16 14:59:29 -07:00
George Rennie 381381c997 write_firrtl: clear used names cache each pass 2025-07-15 14:14:07 +01:00
Akash Levy 082adf8684
Merge branch 'YosysHQ:main' into main 2025-07-15 00:04:28 -04:00
Emil J. Tywoniak 2b659626a3 rename: add -unescape 2025-06-24 12:33:33 +02:00
Akash Levy e3a6b920d4
Merge branch 'YosysHQ:main' into main 2025-06-02 18:47:14 +02:00
Emil J c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs 
aiger: fix -map and -vmap
 2025-06-02 15:07:19 +02:00
N. Engelhardt 1c742441db
Merge pull request #5150 from YosysHQ/krys/aiger_ordering 2025-06-02 13:06:36 +00:00
Krystine Sherwin aac562d36a
aiger.cc: Explicit unsorted-pool-as-LIFO 2025-05-31 09:55:00 +12:00
Krystine Sherwin 0072a267cc
write_aiger: Add no-sort option 
Prevents sorting input/output bits so that they remain in the same order they were read in.
 2025-05-29 16:20:16 +12:00
Akash Levy 3fc74be3e2
Merge branch 'YosysHQ:main' into main 2025-05-28 01:54:49 +02:00
gatecat 45a6940f40 cxxrtl: Add debug items for state with private names 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-05-26 16:58:13 +02:00
Akash Levy 3a23e772dd
Merge branch 'YosysHQ:main' into main 2025-05-24 12:11:52 -07:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
Emil J. Tywoniak f73c6a9c9a write_verilog: don't dump single_bit_vector attribute 2025-05-12 13:36:25 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Akash Levy aeed1ddb74 Update from upstream 2025-05-11 15:16:52 -07:00
Emil J. Tywoniak 2522bcd492 aiger: fix -map and -vmap 2025-05-09 14:21:10 +02:00
Emil J. Tywoniak 90a2c92370 driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
Akash Levy 7191be492c
Merge branch 'YosysHQ:main' into main 2025-05-05 15:36:40 -07:00
Emil J. Tywoniak d7affb8821 driver: add --no-version to suppress writing Yosys version in command outputs 2025-05-05 13:12:08 +02:00
sdjasj da1ac9ae47
cxxrtl: fix missing sign extension before shift operation for signed values 2025-05-03 09:38:16 +00:00
Akash Levy 94bc6937d3
Merge branch 'YosysHQ:main' into main 2025-04-27 15:24:30 -07:00
Catherine 3d1f2161dc cxxrtl: strip `$paramod` from module name in scope info. 2025-04-26 14:51:21 +01:00
Akash Levy b8ee17e807
Merge branch 'YosysHQ:main' into main 2025-04-24 14:51:28 -07:00
sdjasj b693947834 fix udivmod crashes when operand value exceeds logical width 2025-04-24 14:33:52 +01:00
Akash Levy 5f5ed1b29e Merge upstream yosys 2025-04-21 17:36:24 -07:00
David Sawatzke 04098933c7 cxxrtl: Add internal cell "bwmux" 
Mirrors the implementation for the smt2 backend

Co-authored-by: Martin Povišer <povik@cutebit.org>
 2025-04-16 13:58:08 +01:00
Akash Levy e241c9d513
Merge branch 'YosysHQ:main' into main 2025-04-10 14:28:10 -07:00
Krystine Sherwin cd3b914132
Reinstate #4768 
Revert the reversion so that we can fix the bugs that the PR missed.
 2025-04-08 11:58:05 +12:00