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Merge branch 'YosysHQ:main' into main

This commit is contained in:
Akash Levy 2025-08-11 09:26:32 -07:00 committed by GitHub
parent d0ab898e88 2d90e80b52
commit 3733ad3879
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1 changed files with 9 additions and 1 deletions
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10
backends/verilog/verilog_backend.cc
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@ -2391,8 +2391,16 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
f << indent + " " << "reg " << id(initial_id) << " = 0;\n";
}
for (auto w : module->wires())
// first dump input / output according to their order in module->ports
for (auto port : module->ports)
dump_wire(f, indent + " ", module->wire(port));
for (auto w : module->wires()) {
// avoid duplication
if (w->port_id)
continue;
dump_wire(f, indent + " ", w);
}
for (auto &mem : Mem::get_all_memories(module))
dump_memory(f, indent + " ", mem);