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Commit Graph
2191 Commits
Author SHA1 Message Date
Emil J. Tywoniak 5b0023b476 ffmerge: initvals signorm compatibility fixup 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 1336ca079e timinginfo: special-case $specify2 in signorm invariant 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 610c560a2a opt_dff: sigma harder, FfDataSigMapped 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 49548b2648 ff: add FfDataSigMapped 2026-09-17 14:23:07 +02:00
Emil J. Tywoniak 6dd987ee3c signorm: remove $input cells when leaving 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 3a606ec48e signorm: skip const when fixing fanout 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 41d4c1da36 satgen: support $connect 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 8d8a1cb46c rtlil: add dump_sigmap for hacky signorm debugging 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak a55244ee3c timinginfo: disable output wire check due to signorm 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 196cb50038 rtlil: forbid rewrite_sigspecs in signorm 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 42a9ec0dba ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire 2026-09-17 14:12:38 +02:00
Emil J. Tywoniak 6f27925eff rtlil: fix zero width SigSpec crash in signorm setPort unsetPort 2026-09-17 14:12:38 +02:00
Emil J. Tywoniak 696f7dc173 rtlil_bufnorm: fix cell deletion deferral bug 2026-09-17 14:12:38 +02:00
Emil J. Tywoniak f2fbfbb512 mem: fix signorm cell type morph 2026-09-17 14:12:38 +02:00
Jannis Harder 52ec5579fb WIP half broken snapshot 2026-09-17 14:12:36 +02:00
Jannis Harder 3c2b04a01b WIP remove dead code 2026-09-17 14:10:46 +02:00
Miodrag Milanović f1442ce42e Merge pull request #6182 from YosysHQ/lofty/revert-read_xaiger2 
Temporarily revert #6101 and #6077
 2026-09-08 04:53:08 +00:00
Lofty 51583d854a Revert "Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8" 
This reverts commit fd6367405e, reversing
changes made to 0f2bcb94b7.
 2026-09-07 17:29:08 +01:00
nella 7c26ff16c6 Merge pull request #6162 from YosysHQ/nella/scl-cache-dir 
liberty_cache: per user SCL cache directory [sc-843]
 2026-09-07 14:52:21 +00:00
Miodrag Milanovic 756434cc23 cmake: replace -Werror=unused with more specific options 2026-09-07 11:27:12 +02:00
Emil J edb882e874 Merge pull request #6177 from YosysHQ/emil/abc-prepare-extract-sequence-determinism-2 
abc: isolate state mutation in prepare and extract for multi-threaded determinism
 2026-09-04 13:09:37 +00:00
Emil J. Tywoniak 3870f810f3 kernel: avoid running ensure_at_least in parallel 2026-09-04 11:11:55 +02:00
Miodrag Milanović 28b7a17675 Merge pull request #6115 from YosysHQ/log-sink 
log rewrite [sc-748]
 2026-09-02 13:03:29 +00:00
nella 9c2e1a8338 Add scl cache dir option. 2026-09-01 14:29:02 +02:00
Miodrag Milanovic 726aff678f log: remove log_ prefix and unified some namings 2026-08-31 11:20:21 +02:00
Miodrag Milanovic 09c227b0a7 log_stderr_sink_forced since it is external sink configuration 2026-08-31 10:34:45 +02:00
Miodrag Milanovic cdb5ff5f99 log: keep log_debug a macro 2026-08-31 08:25:47 +02:00
nella d26f1a8573 Review fixups 
Co-authored-by: Emil J. Tywoniak <[email protected]>
 2026-08-27 23:10:40 +06:00
nella 2c40c4ea13 Readd seeding comment. 2026-08-27 15:16:48 +02:00
nella f0236d8d20 Move module seeding into Design::add. 2026-08-27 14:34:10 +02:00
nella 5ff5eeb9f8 Fix bufnorm edge cases. 2026-08-26 16:08:45 +02:00
Miodrag Milanovic b3e25aea62 log: couple of fixes 2026-08-26 12:27:29 +02:00
Miodrag Milanovic a3cc43277f log: added log_deprecated 2026-08-26 08:40:12 +02:00
tangxifan 02dc5a82d7 [core] add a cmake option to disable unit test during compilation; Use cmake_current_source for submodule integration 
[core] debug yosys version extraction

[core] debug

[core] now cache the cmake source dir

[core] debug

[core] debug kernel dependencies

[core] debug common include directories

[core] debug

[core] debug simlib_help.inc

[core] debug pmgen py path in cmake

[core] syntax

[core] debug flex source

[core] restore

[core] debug executable output as it now shows linking to .

[core] debug yosys-abc directory

[core] debug cmake share directory

[core] debug yosys abc

[core] restore shared directory location as yosys requires fixed location

[core] rework link target to yosys sub dir under build

[core] fixed the bug on yosys-config.install location for install

[core] cmake syntax

[core] correct the location for share directory

[core] debug

[core] debug

[core] debug

[core] enforce internal attributes; rename the YOSYS_ENABLE_UNIT_TESTS; use YOSYS_CMAKE_BINARY_DIR for all

[core] apply review comments

[core] rename

[core] change all the CMAKE_BINARY_DIR to YOSYS_CMAKE_BINARY_DIR

[core] replace CMAKE_SOURCE_DIR to YOSYS_CMAKE_SOURCE_DIR
 2026-08-21 12:09:04 -07:00
Miodrag Milanovic 14f85ce38e log: updating review point 2026-08-21 13:25:47 +02:00
Miodrag Milanovic 900fd36eec log: small cleanup 2026-08-21 09:19:56 +02:00
Miodrag Milanovic 01f63a6367 log: header is one message, but only content is compared in match 2026-08-21 08:12:07 +02:00
Miodrag Milanovic caad7779e0 log: propagate format information 2026-08-20 17:30:44 +02:00
Miodrag Milanovic 17c2846cda log: first line should have printed timestamp 2026-08-20 15:29:43 +02:00
Miodrag Milanovic bd1c3942aa log: remove non-useful/non-used functionality 2026-08-20 15:19:36 +02:00
Miodrag Milanovic f63d90003e log: not needed anymore after using singleton 2026-08-20 09:16:28 +02:00
Miodrag Milanovic 3bd81c2bd2 log: make initial time as before and some cleanup 2026-08-19 17:25:13 +02:00
Miodrag Milanovic 2e113f5eff log: create LogManager singleton and move implementation 2026-08-19 15:59:46 +02:00
nellaandMike Inouye 38b6e5e76c fix WASI, harden scl cache locking. 
Co-authored-by: Mike Inouye <[email protected]>
 2026-08-18 11:31:57 +02:00
nella cd029c0638 Add solve without model. 2026-08-17 12:19:07 +02:00
Miodrag Milanovic b17b5a19e0 log: fix some functionality and wrappers 2026-08-14 12:23:25 +02:00
Miodrag Milanovic cbbd8c0dfd log: convert all to sinks 2026-08-14 11:55:46 +02:00
Miodrag Milanovic bd5c524dc6 log: do it over callback so we can experiment 2026-08-13 12:37:58 +02:00
Miodrag Milanovic 10bfedd4ac log: convert some messages to log_comment 2026-08-13 09:22:12 +02:00
Miodrag Milanovic 14afc00862 log: Refactor code a bit more 2026-08-13 09:22:01 +02:00