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1743 Commits

Author SHA1 Message Date
N. Engelhardt 81f87ce6ed
Revert "Add groups to command reference" 2025-07-23 14:41:49 +00:00
Robert O'Callahan f25f8fe7c4 In the Verilog backend, only sort modules that we're going to emit. 
If you have a large design with a lot of modules and you use the Verilog
backend to emit modules one at a time to separate files, performance is
very low. The problem is that the Verilog backend calls `design->sort()`
every time, which sorts the contents of all modules, and this is slow
even when everything is already sorted.

We can easily fix this by only sorting the contents of modules that
we're actually going to emit.
 2025-07-21 05:32:31 +00:00
Krystine Sherwin d62a110dc8
register.h: Add internal_flag to Pass 
Update experimental pass warnings to use a shared function.  Reduces repetition, and also allows all of the warning flags to be combined (which at present is just experimental and the new internal).
Update `test_*` passes to call `internal()` in their constructors.
 2025-07-21 10:35:19 +12:00
Akash Levy 37806d5ea7
Merge branch 'YosysHQ:main' into main 2025-07-16 14:59:29 -07:00
George Rennie 381381c997 write_firrtl: clear used names cache each pass 2025-07-15 14:14:07 +01:00
Akash Levy 082adf8684
Merge branch 'YosysHQ:main' into main 2025-07-15 00:04:28 -04:00
Emil J. Tywoniak 2b659626a3 rename: add -unescape 2025-06-24 12:33:33 +02:00
Akash Levy e3a6b920d4
Merge branch 'YosysHQ:main' into main 2025-06-02 18:47:14 +02:00
Emil J c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs 
aiger: fix -map and -vmap
 2025-06-02 15:07:19 +02:00
N. Engelhardt 1c742441db
Merge pull request #5150 from YosysHQ/krys/aiger_ordering 2025-06-02 13:06:36 +00:00
Krystine Sherwin aac562d36a
aiger.cc: Explicit unsorted-pool-as-LIFO 2025-05-31 09:55:00 +12:00
Krystine Sherwin 0072a267cc
write_aiger: Add no-sort option 
Prevents sorting input/output bits so that they remain in the same order they were read in.
 2025-05-29 16:20:16 +12:00
Akash Levy 3fc74be3e2
Merge branch 'YosysHQ:main' into main 2025-05-28 01:54:49 +02:00
gatecat 45a6940f40 cxxrtl: Add debug items for state with private names 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-05-26 16:58:13 +02:00
Akash Levy 3a23e772dd
Merge branch 'YosysHQ:main' into main 2025-05-24 12:11:52 -07:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
Emil J. Tywoniak f73c6a9c9a write_verilog: don't dump single_bit_vector attribute 2025-05-12 13:36:25 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Akash Levy aeed1ddb74 Update from upstream 2025-05-11 15:16:52 -07:00
Emil J. Tywoniak 2522bcd492 aiger: fix -map and -vmap 2025-05-09 14:21:10 +02:00
Emil J. Tywoniak 90a2c92370 driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
Akash Levy 7191be492c
Merge branch 'YosysHQ:main' into main 2025-05-05 15:36:40 -07:00
Emil J. Tywoniak d7affb8821 driver: add --no-version to suppress writing Yosys version in command outputs 2025-05-05 13:12:08 +02:00
sdjasj da1ac9ae47
cxxrtl: fix missing sign extension before shift operation for signed values 2025-05-03 09:38:16 +00:00
Akash Levy 94bc6937d3
Merge branch 'YosysHQ:main' into main 2025-04-27 15:24:30 -07:00
Catherine 3d1f2161dc cxxrtl: strip `$paramod` from module name in scope info. 2025-04-26 14:51:21 +01:00
Akash Levy b8ee17e807
Merge branch 'YosysHQ:main' into main 2025-04-24 14:51:28 -07:00
sdjasj b693947834 fix udivmod crashes when operand value exceeds logical width 2025-04-24 14:33:52 +01:00
Akash Levy 5f5ed1b29e Merge upstream yosys 2025-04-21 17:36:24 -07:00
David Sawatzke 04098933c7 cxxrtl: Add internal cell "bwmux" 
Mirrors the implementation for the smt2 backend

Co-authored-by: Martin Povišer <povik@cutebit.org>
 2025-04-16 13:58:08 +01:00
Akash Levy e241c9d513
Merge branch 'YosysHQ:main' into main 2025-04-10 14:28:10 -07:00
Krystine Sherwin cd3b914132
Reinstate #4768 
Revert the reversion so that we can fix the bugs that the PR missed.
 2025-04-08 11:58:05 +12:00
Akash Levy 06c614a010
Merge branch 'YosysHQ:main' into main 2025-04-07 07:28:06 -07:00
Miodrag Milanović d49364d96f
Revert "Refactor full_selection" 2025-04-07 12:11:55 +02:00
Akash Levy 0dab4308a3 Actual merge here 2025-04-06 18:53:43 -07:00
KrystalDelusion 98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections 
Refactor full_selection
 2025-04-05 14:15:27 +13:00
Akash Levy f218b5ba58 Revert "Represent memory size with size_t" 
This reverts commit bb5f8415af.
 2025-04-04 03:20:07 -07:00
Akash Levy bb5f8415af Represent memory size with size_t 2025-04-04 02:04:34 -07:00
Akash Levy 95f489beec Merge nice gzip refactor 2025-03-20 16:47:12 -07:00
Emil J. Tywoniak 4f3fdc8457 io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
Akash Levy 1c0d4a43b3
Merge branch 'YosysHQ:main' into main 2025-03-14 18:07:55 -07:00
KrystalDelusion 9fa1f0e70c
Merge pull request #4567 from kivikakk/cxxrtl-escape-trailing 
cxxrtl: use octal encoding of non-printables.
 2025-03-14 16:52:07 +13:00
Krystine Sherwin 46a311acb2
firrtl: Drop full_selection check 
Change `top` pointer default to `nullptr` to avoid issues with `Design->top_module()` only operating on the current selection.

Calls to other passes (`bmuxmap` etc) will only operate on the current selection, and may cause problems when those cells are unprocessed, but this is consistent with the other backends that only operate on the full designs and will hopefully be fixed in another PR soon :)
 2025-03-14 14:08:56 +13:00
Krystine Sherwin dac2bb7d4d
Use selection helpers 
Catch more uses of selection constructor without assigning a design.
 2025-03-14 14:08:13 +13:00
Akash Levy e4066b784d Merge remote-tracking branch 'upstream/main' 2025-03-12 19:21:32 -07:00
KrystalDelusion 65748b8387
Merge pull request #4898 from Anhijkt/fix-xaiger-segfault 
write_xaiger: Detect and error on combinatorial loops
 2025-03-13 10:49:48 +13:00
Akash Levy e360511339
Merge branch 'YosysHQ:main' into main 2025-03-10 14:21:49 -07:00
Alain Dargelas 268459e00a write_verilog -srcattronly option 2025-03-10 10:15:24 -07:00
Alain Dargelas 1b1882fe56 write_verilog -srcattronly option 2025-03-10 09:29:48 -07:00
Alain Dargelas e35032f2f6 write_verilog -onlysrcattr option 2025-03-10 09:27:27 -07:00
N. Engelhardt c74df780b7
Merge pull request #4884 from YosysHQ/docs-preview-functional_tutorial 
Docs: More on FunctionalIR
 2025-03-10 15:05:55 +00:00
Anhijkt a8052f653a write_xaiger: Detect and error on combinatorial loops 2025-02-14 01:21:39 +02:00
Krystine Sherwin fa2d45a922
smtr: Refactor write back into _eval and _initial 
Easier for comparisons, and the structure still works.  (I don't remember why I moved away from it in the first place.)
 2025-02-07 13:58:09 +13:00
Akash Levy 66186f11fd
Merge branch 'YosysHQ:main' into main 2025-01-30 14:00:19 -08:00
Robin Ole Heinemann 0ab13924a5 write_verilog: log_abort on unhandled $check flavor 2025-01-30 14:18:02 +00:00
Robin Ole Heinemann 2f11dc87c9 write_verilog: emit $check cell names as labels 2025-01-30 14:18:02 +00:00
Akash Levy f403256a34
Merge branch 'YosysHQ:main' into main 2025-01-23 14:06:16 -08:00
Catherine 3076803c9e
write_json: missing \n in help text. 2025-01-23 05:17:52 +00:00
Akash Levy 5c514e00a4 Sync with upstream 2025-01-13 17:20:59 -08:00
N. Engelhardt 77b28442a5 emit $scopeinfo cells by default 2025-01-08 14:47:46 +01:00
N. Engelhardt dab7905cbe write_json: add option to include $scopeinfo cells 2025-01-08 13:33:56 +01:00
Krystine Sherwin 7698dfba5e
smtr: Fix help text 
Can't take both [selection] and [filename] optional arguments.
 2025-01-06 14:31:50 +13:00
Akash Levy 33b3d933de
Merge branch 'YosysHQ:main' into main 2024-12-25 04:25:25 -08:00
Catherine 1ef4c7f565
yosys-smtbmc: add cvc5 to help text. 2024-12-25 04:59:02 +00:00
Akash Levy 1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J. Tywoniak d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
Akash Levy caaef5ac14
Merge branch 'YosysHQ:main' into main 2024-12-11 12:00:34 -08:00
Martin Povišer 86fad8f6f5
Merge pull request #4803 from povik/write_verilog-buf 
write_verilog: Use assign for `$buf`
 2024-12-10 20:10:58 +01:00
Martin Povišer 559209c856 abc_new: Fix PI confusion in whitebox model export 2024-12-10 14:27:29 +01:00
Martin Povišer 495a7805ec aiger2: Support `$extern:` hierarchy 
`$extern:...` modules inserted by `techmap -extern` are special in the
regard that they have a private ID (starting with a dollar sign) but are
not an internal cell. Support those modules in xaiger export.
 2024-12-10 14:27:29 +01:00
Martin Povišer e7b21d2706 write_verilog: Use assign for `$buf` 2024-12-05 18:28:23 +01:00
Akash Levy 4356eae4c9 Yosys sync 2024-12-04 14:16:55 -08:00
Krystine Sherwin e634e9c26b
aiger2: Resolve warnings 
- Remove unused statics CONST_FALSE and CONST_TRUE (which appear to have been folded into the `Index` declaration as CFALSE and CTRUE).
- Assign default value of EMPTY_LIT to `a` and `b` for comparison ops.
- Tag debug only variables with YS_MAYBE_UNUSED, don't assign unused variables (but continue to call the function because it moves the file pointer).
 2024-12-03 14:01:57 +13:00
Krystine Sherwin 1de5d98ae2
Reduce comparisons of size_t and int 
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
 2024-11-29 12:53:29 +13:00
Akash Levy 1a69c51c88
Merge branch 'YosysHQ:main' into main 2024-11-18 16:10:30 -08:00
KrystalDelusion dcff8b0666
Merge pull request #4719 from AdamLee7/main 
add select option for write_json
 2024-11-19 08:42:38 +13:00
Akash Levy 5210d8614c Merge 2024-11-17 22:46:05 -08:00
Akash Levy ace558e90c Simplify using module->ports, which is apparently sorted 2024-11-17 11:36:30 -08:00
Akash Levy 3a32729373 Remove keep_running variable (unused) 2024-11-17 10:40:04 -08:00
Akash Levy 8f9a0b680a Fix O(N^2) port dump down to O(N) 2024-11-16 22:56:41 -08:00
Alain Dargelas 88c847f733 Oopsy! 2024-11-16 17:04:07 -08:00
Alain Dargelas f011b74f87 Fix port dump n^2 -> n 2024-11-16 10:43:25 -08:00
Akash Levy 6be73e5c2e Updates 2024-11-15 19:02:06 -08:00
George Rennie d7c6688905 write_btor: support $_BUF_ 2024-11-15 11:47:09 +01:00
Robin Ole Heinemann 6d4f056a35 cxxrtl: use debug attrs of alias not aliasee 2024-11-12 13:07:33 +00:00
Akash Levy ea76abdaee Merge 2024-11-11 11:47:58 -08:00
Robin Ole Heinemann 8bc4bd8a20 cxxrtl, fmt: escape double quotes in c strings 2024-11-11 18:49:05 +00:00
Jannis Harder 558b2f9ae9
Merge pull request #3953 from georgerennie/bug_3769 
write_smt2: Check for constant bool after fully resolving signal
 2024-11-11 16:23:35 +01:00
Jannis Harder 014cb531aa
Merge pull request #4645 from georgerennie/george/btor_undef_array_init 
write_btor: only initialize array with const value when it is fully def
 2024-11-11 16:18:57 +01:00
Jannis Harder 261b44718d
Merge pull request #4641 from georgerennie/george/btor_undriven_wires 
write_btor: don't emit undriven bits multiple times
 2024-11-11 16:17:25 +01:00
Akash Levy fa50434708
Merge branch 'YosysHQ:main' into main 2024-11-08 14:10:24 -08:00
AdamLee7 7ed359fa7b add select option for write_json 2024-11-07 17:48:06 +08:00
George Rennie 9047290683 write_btor: support $buf 
* treated the same as $pos
 2024-11-06 19:49:09 +01:00
Krystine Sherwin ee73a91f44
Remove references to ilang 2024-11-05 12:36:31 +13:00
Akash Levy d63c793e72
Merge branch 'YosysHQ:main' into main 2024-10-28 11:24:55 -07:00
Martin Povišer 598f6c9de9 aiger2: Fix open-coded constants 2024-10-26 08:54:01 +02:00
Akash Levy 97a804ac12 Split large constants onto new lines in verilog backend 2024-10-25 15:52:19 -07:00
Akash Levy 1953a42f0d Add new lines 2024-10-23 23:52:55 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Jean-François Nguyen f953a516d0 cxxrtl: fix handling of 0-bit variables in `vcd_writer.sample()`. 2024-10-13 01:00:40 +01:00