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241 Commits

Author SHA1 Message Date
Akash Levy a90a5e10d6
Merge branch 'YosysHQ:main' into main 2025-11-18 11:48:04 -05:00
Robert O'Callahan b870693393 Fix reset_auto_counter_id to correctly detect _NNN_ patterns 
This fixes a regression caused by commit c4c389fdd7.
 2025-11-17 09:21:59 +00:00
Akash Levy 71586d39b0 Merge from upstream 2025-11-12 08:14:33 -08:00
Robert O'Callahan c4c389fdd7 Fix verilog backend to avoid IdString::c_str() 2025-11-12 11:52:04 +01:00
Akash Levy 950c619569 Smallfixes 2025-11-11 23:50:04 -08:00
Akash Levy e21324d609 Merge from upstream 2025-11-11 22:52:11 -08:00
Robert O'Callahan 92ea557979 Build a temporary SigChunk list in the iterator in the cases where that's needed 2025-11-07 15:54:55 +00:00
Akash Levy 60d969530b Bump to latest 2025-09-21 01:10:04 -07:00
Jannis Harder 79e05a195d verilog: Bufnorm cell backend and frontend support 
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
 2025-09-17 14:01:09 +02:00
Robert O'Callahan d24488d3a5 Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff() 2025-09-17 03:24:19 +00:00
Robert O'Callahan 34df6569a6 Update backends to avoid bits() 2025-09-16 03:17:23 +00:00
Akash Levy f5cb0c328f Bump Yosys to latest 2025-09-13 04:35:52 -07:00
Robert O'Callahan e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Akash Levy 1b3375d8df Merge upstream in 2025-09-09 05:50:48 -07:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Akash Levy 3733ad3879
Merge branch 'YosysHQ:main' into main 2025-08-11 09:26:32 -07:00
Hongce Zhang 76e507f307 update verilog_backend according to Github comments 2025-08-08 16:17:37 +08:00
Hongce Zhang 3cbbb9456d reorder verilog backend port wires 2025-08-07 11:37:23 +08:00
Akash Levy cc733fd11b Merge from upstream 2025-07-30 22:50:14 -07:00
Miodrag Milanović 1d229ae254
Merge pull request #5221 from rocallahan/typed-stringf 
Introduce variadic template implementation of `stringf` that supports `std::string` parameters
 2025-07-29 15:12:49 +02:00
Robert O'Callahan 6ee3cd8ffd Replace `stringf()` with a templated function which does compile-time format string checking. 
Checking only happens at compile time if -std=c++20 (or greater) is enabled. Otherwise
the checking happens at run time.

This requires the format string to be a compile-time constant (when compiling with
C++20), so fix a few places where that isn't true.

The format string behavior is a bit more lenient than C printf. For %d/%u
you can pass any integer type and it will be converted and output without
truncating bits, i.e. any length specifier is ignored and the conversion is
always treated as 'll'. Any truncation needs to be done by casting the argument itself.
For %f/%g you can pass anything that converts to double, including integers.

Performance results with clang 19 -O3 on Linux:
```
hyperfine './yosys -dp "read_rtlil /usr/local/google/home/rocallahan/Downloads/jpeg.synth.il; dump"'
```
C++17 before: Time (mean ± σ):     101.3 ms ±   0.8 ms    [User: 85.6 ms, System: 15.6 ms]
C++17 after:  Time (mean ± σ):      98.4 ms ±   1.2 ms    [User: 82.1 ms, System: 16.1 ms]
C++20 before: Time (mean ± σ):     100.9 ms ±   1.1 ms    [User: 87.0 ms, System: 13.8 ms]
C++20 after:  Time (mean ± σ):      97.8 ms ±   1.4 ms    [User: 83.1 ms, System: 14.7 ms]

The generated code is reasonably efficient. E.g. with clang 19, `stringf()` with a format
with no %% escapes and no other parameters (a weirdly common case) often compiles to a fully
inlined `std::string` construction. In general the format string parsing is often (not always)
compiled away.
 2025-07-29 05:29:33 +00:00
Robert O'Callahan f25f8fe7c4 In the Verilog backend, only sort modules that we're going to emit. 
If you have a large design with a lot of modules and you use the Verilog
backend to emit modules one at a time to separate files, performance is
very low. The problem is that the Verilog backend calls `design->sort()`
every time, which sorts the contents of all modules, and this is slow
even when everything is already sorted.

We can easily fix this by only sorting the contents of modules that
we're actually going to emit.
 2025-07-21 05:32:31 +00:00
Akash Levy 082adf8684
Merge branch 'YosysHQ:main' into main 2025-07-15 00:04:28 -04:00
Emil J. Tywoniak 2b659626a3 rename: add -unescape 2025-06-24 12:33:33 +02:00
Akash Levy 3a23e772dd
Merge branch 'YosysHQ:main' into main 2025-05-24 12:11:52 -07:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
Emil J. Tywoniak f73c6a9c9a write_verilog: don't dump single_bit_vector attribute 2025-05-12 13:36:25 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Akash Levy aeed1ddb74 Update from upstream 2025-05-11 15:16:52 -07:00
Emil J. Tywoniak 90a2c92370 driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
Emil J. Tywoniak d7affb8821 driver: add --no-version to suppress writing Yosys version in command outputs 2025-05-05 13:12:08 +02:00
Akash Levy f218b5ba58 Revert "Represent memory size with size_t" 
This reverts commit bb5f8415af.
 2025-04-04 03:20:07 -07:00
Akash Levy bb5f8415af Represent memory size with size_t 2025-04-04 02:04:34 -07:00
Alain Dargelas 268459e00a write_verilog -srcattronly option 2025-03-10 10:15:24 -07:00
Alain Dargelas 1b1882fe56 write_verilog -srcattronly option 2025-03-10 09:29:48 -07:00
Alain Dargelas e35032f2f6 write_verilog -onlysrcattr option 2025-03-10 09:27:27 -07:00
Akash Levy 66186f11fd
Merge branch 'YosysHQ:main' into main 2025-01-30 14:00:19 -08:00
Robin Ole Heinemann 0ab13924a5 write_verilog: log_abort on unhandled $check flavor 2025-01-30 14:18:02 +00:00
Robin Ole Heinemann 2f11dc87c9 write_verilog: emit $check cell names as labels 2025-01-30 14:18:02 +00:00
Akash Levy caaef5ac14
Merge branch 'YosysHQ:main' into main 2024-12-11 12:00:34 -08:00
Martin Povišer e7b21d2706 write_verilog: Use assign for `$buf` 2024-12-05 18:28:23 +01:00
Akash Levy 5210d8614c Merge 2024-11-17 22:46:05 -08:00
Akash Levy ace558e90c Simplify using module->ports, which is apparently sorted 2024-11-17 11:36:30 -08:00
Akash Levy 3a32729373 Remove keep_running variable (unused) 2024-11-17 10:40:04 -08:00
Akash Levy 8f9a0b680a Fix O(N^2) port dump down to O(N) 2024-11-16 22:56:41 -08:00
Alain Dargelas 88c847f733 Oopsy! 2024-11-16 17:04:07 -08:00
Alain Dargelas f011b74f87 Fix port dump n^2 -> n 2024-11-16 10:43:25 -08:00
Akash Levy 97a804ac12 Split large constants onto new lines in verilog backend 2024-10-25 15:52:19 -07:00
Akash Levy 1953a42f0d Add new lines 2024-10-23 23:52:55 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00