luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Smallfixes

This commit is contained in:
Akash Levy 2025-11-11 23:50:04 -08:00
parent e21324d609
commit 950c619569
2 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
backends/verilog/verilog_backend.cc
View File

@ -381,12 +381,13 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
if (sig.is_fully_const() && GetSize(sig) > 8192) {
f << stringf("{ ");
int i = 0;
for (auto it = sig.bits().rbegin(); it != sig.bits().rend(); ++it) {
auto chunks = sig.chunks();
for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
dump_const(f, it->data, 1, 0);
if (it != sig.bits().rend() - 1)
if (it != chunks.rbegin())
f << stringf(", ");
if (i++ % 20 == 19)
f << stringf("\n");
f << stringf("\n");
}
f << stringf(" }");
return;

9
kernel/rtlil.cc
View File

@ -5492,12 +5492,11 @@ bool RTLIL::SigSpec::is_mostly_const() const
{
cover("kernel.rtlil.sigspec.is_mostly_const");
pack();
int constbits = 0;
for (auto it = chunks_.begin(); it != chunks_.end(); it++)
if (it->width > 0 && it->wire == NULL)
constbits += it->width;
return (constbits > width_/2);
for (auto &chunk : chunks())
if (chunk.width > 0 && chunk.wire == NULL)
constbits += chunk.width;
return (constbits > size()/2);
}
bool RTLIL::SigSpec::known_driver() const