Commit Graph
17768 Commits
Author SHA1 Message Date
Lofty a6790877e4 fix dsp.ys 2026-09-03 13:28:38 +01:00
Lofty e35d4bcc15 fix meminit.ys 2026-09-03 13:24:37 +01:00
nella ad5f80bf0d Drop replaced box. 2026-09-03 14:16:31 +02:00
nella 0757499542 Handle inout and unresolved box port dirs. 2026-09-02 13:49:01 +02:00
Lofty b91ba79819 add comment 2026-09-02 11:23:05 +01:00
Lofty 07a1097f47 improve wording 2026-09-02 11:10:11 +01:00
Lofty 24c39f1121 clarify bad connection error message 2026-09-02 11:08:17 +01:00
nella 286ce13ff2 Use pre-bufnorm net name. 2026-09-02 11:47:24 +02:00
Lofty 85c930f64d update tests 2026-09-01 12:47:01 +01:00
Lofty 3f71c16f1b punt xaiger2 -dff to another PR 2026-09-01 12:47:01 +01:00
nella 262b9f59f6 Quieten box connection warnings. 2026-09-01 12:47:01 +01:00
nella 98dcab773b Lazy mux selects, detect cycles. 2026-09-01 12:47:01 +01:00
nella e741bd009f Add shift, mul, eqx to aiger2. 2026-09-01 12:47:01 +01:00
Lofty 4c4d85e0d4 scratchpad option for xaiger1 2026-09-01 12:47:01 +01:00
Lofty 7c4d0b4b97 update tests 2026-09-01 12:47:01 +01:00
nella 569e454ccf Fix box models and output order. 2026-09-01 12:47:01 +01:00
Lofty 66b8e7e34a no need to aigmap anymore 2026-09-01 12:47:01 +01:00
Lofty 3e31de7881 adjust add_sub.ys 2026-09-01 12:47:01 +01:00
nella 9a86e65d80 Order carry ports last. 2026-09-01 12:47:01 +01:00
nella 567a0f95de Emit a bit index on map2 box records. 2026-09-01 12:47:01 +01:00
Lofty a24214a38a fill out some scratchpad fields 2026-09-01 12:47:01 +01:00
nella 7cdcf7e3e0 Handle boxes without a whitebox model. 2026-09-01 12:47:01 +01:00
Lofty 184ff2d0de abc9: migrate to write_xaiger2 2026-09-01 12:47:01 +01:00
Miodrag Milanović 56cf2cf419 Merge pull request #6159 from YosysHQ/mmicko/update_sv_elab
Update sv-elab to release 2026-08-30
2026-09-01 06:37:05 +00:00
Miodrag Milanovic 7c10ee1c58 Update sv-elab as of 2026-09-01 2026-09-01 08:20:05 +02:00
nella c30457480f Merge pull request #6155 from YosysHQ/nella/xaiger2-bufnorm-edgecases
ABCU: fix bufnorm edge cases
2026-08-27 15:08:19 +00:00
nella 2c40c4ea13 Readd seeding comment. 2026-08-27 15:16:48 +02:00
nella f0236d8d20 Move module seeding into Design::add. 2026-08-27 14:34:10 +02:00
nella 5ff5eeb9f8 Fix bufnorm edge cases. 2026-08-26 16:08:45 +02:00
Miodrag Milanović 13b43f8c85 Merge pull request #6149 from YosysHQ/mmicko/cxxheaderparser
pyosys: Check for required cxxheaderparser version, fixes #5974
2026-08-26 06:01:37 +00:00
Miodrag Milanovic ab2610b816 pyosys: Check for required cxxheaderparser version, fixes #5974 2026-08-25 13:37:56 +02:00
Emil J dd83bbad28 Merge pull request #6116 from antmicro/mgan/hdlname-fix
Fix ignored `hdlname` attribute in `dfflibmap` pass
2026-08-24 11:36:17 +00:00
Emil J e3af33003d Merge pull request #6141 from john-kearney/fix-json-netnames-signed
json: read 'signed' on netnames, matching ports
2026-08-24 10:19:44 +00:00
Emil J 85acd07685 Merge pull request #6123 from sifferman/fix-resetall-default-nettype
Fix resetall not affecting default_nettype
2026-08-24 09:47:04 +00:00
Miodrag Milanović 2e1666cd82 Merge pull request #6147 from YosysHQ/mmicko/cleanup
cleanup: remove status message
2026-08-24 09:41:29 +00:00
Miodrag Milanovic 1643567be6 cleanup: remove status message 2026-08-24 11:23:35 +02:00
Miodrag Milanović 47bbdab297 Merge pull request #6139 from tangxifan/xt_openfpga_cmake
Support Yosys built as a subdirectory
2026-08-24 07:16:21 +00:00
tangxifan 02dc5a82d7 [core] add a cmake option to disable unit test during compilation; Use cmake_current_source for submodule integration
[core] debug yosys version extraction

[core] debug

[core] now cache the cmake source dir

[core] debug

[core] debug kernel dependencies

[core] debug common include directories

[core] debug

[core] debug simlib_help.inc

[core] debug pmgen py path in cmake

[core] syntax

[core] debug flex source

[core] restore

[core] debug executable output as it now shows linking to .

[core] debug yosys-abc directory

[core] debug cmake share directory

[core] debug yosys abc

[core] restore shared directory location as yosys requires fixed location

[core] rework link target to yosys sub dir under build

[core] fixed the bug on yosys-config.install location for install

[core] cmake syntax

[core] correct the location for share directory

[core] debug

[core] debug

[core] debug

[core] enforce internal attributes; rename the YOSYS_ENABLE_UNIT_TESTS; use YOSYS_CMAKE_BINARY_DIR for all

[core] apply review comments

[core] rename

[core] change all the CMAKE_BINARY_DIR to YOSYS_CMAKE_BINARY_DIR

[core] replace CMAKE_SOURCE_DIR to YOSYS_CMAKE_SOURCE_DIR
2026-08-21 12:09:04 -07:00
nella a34d3baae9 Merge pull request #6131 from DanielMBouyou/fix/arith_tree-narrow-intermediate-truncation
arith_tree: don't fold a chain link narrower than its consumer
2026-08-21 09:12:00 +00:00
Daniel M'BOUYOU 25c7053114 arith_tree: add regression tests for truncating narrow chain links
#6130 fixed arith_tree so that a chain link narrower than its consumer
is left out of the tree, and added an equivalence regression for the
exact failing shape. Cover what that test does not: structural checks
that the narrow link survives as its own cell, on both the raw $add
path and the alumacc $alu path, and a mixed case where a wider chain
consuming the truncated link as a leaf still folds and stays
equivalent.

Signed-off-by: Daniel M'BOUYOU <[email protected]>
2026-08-21 10:38:58 +02:00
John Kearney 0f5efca3c9 json: read 'signed' attribute on netnames, matching ports
The JSON backend writes "signed": 1 for any signed wire, including
internal nets. The frontend only parsed the attribute for ports,
so a write-read roundtrip silently cleared is_signed on internal
nets. Signed internal wires became unsigned between the two passes.

Fix: parse 'signed' in the netnames loop, next to the existing
upto/offset handling. Regression test does a full roundtrip and
checks the internal signed wire survives.
2026-08-20 22:20:24 -07:00
Nick Allison 144c707b78 Merge pull request #6117 from Zaneham/check-cells-backends
Error rather than silently drop $check cells in write_smt2 and write_btor
2026-08-20 20:16:36 +00:00
Nick Allison 5c0100c45e Merge branch 'main' into check-cells-backends 2026-08-20 13:07:22 -06:00
Miodrag Milanović 2fd290ad47 Merge pull request #6134 from SimonEbner/main
Retry read operations interrupted by EINTR
2026-08-20 16:24:26 +00:00
Lofty 4ad3dc46ad Merge pull request #6137 from YosysHQ/lofty/abc-refactor-14
synth_gatemate: remove classic ABC mapping for LUTs
2026-08-20 10:33:07 +00:00
Zane Hambly bec454465f Merge branch 'main' into check-cells-backends 2026-08-20 21:42:56 +12:00
Lofty be69f88e55 Merge pull request #6135 from YosysHQ/lofty/abc-refactor-13
abc: remove -sop
2026-08-20 09:34:26 +00:00
nella 59a3826bbd Merge pull request #6130 from DanielMBouyou/arith-tree-narrow-link
arith_tree: do not flatten a chain link narrower than its consumer
2026-08-20 08:40:25 +00:00
Lofty 030e13569c synth_gatemate: remove classic ABC mapping for LUTs 2026-08-20 09:33:47 +01:00
Lofty caceaaa2bb abc: remove -sop 2026-08-19 12:52:10 +01:00