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Quieten box connection warnings.

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nella
2026-09-01 12:47:01 +01:00
committed by Lofty
parent 98dcab773b
commit 262b9f59f6
2 changed files with 3 additions and 2 deletions
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backends/aiger2/aiger.cc
+2 -2
View File
@@ -1430,7 +1430,7 @@ struct XAigerWriter : AigerWriter {
bit = conn[i];
} else {
// FIXME: hierarchical path
log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n",
log_debug("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n",
port_id.unescape(), i, box, box->type.unescape());
bit = RTLIL::Sx;
}
@@ -1466,7 +1466,7 @@ struct XAigerWriter : AigerWriter {
bit = conn[i];
} else {
// FIXME: hierarchical path
log_warning("connection on port %s[%d] of instance %s (type %s) missing\n",
log_debug("connection on port %s[%d] of instance %s (type %s) missing\n",
port_id.unescape(), i, box, box->type.unescape());
pad_pi();
continue;
tests/arch/xilinx/dsp_abc9.ys
+1
View File
@@ -1,5 +1,6 @@
logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*"
logger -nowarn "Ignoring boxed module .*\."
logger -nowarn "Feature 'write_xaiger2' is experimental\."
read_verilog <<EOT
module top(input [24:0] A, input [17:0] B, output [47:0] P);