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17797 Commits

Author SHA1 Message Date
Stan Lee a52689a1fa
Merge branch 'main' into main 2026-01-21 15:46:06 -08:00
Stan Lee 99cf75531f merge 2026-01-21 15:43:25 -08:00
Stan Lee f026cebaf6 address comments 2026-01-21 15:16:45 -08:00
Akash Levy 947139aca1 Remove opt_balance_tree from silimate (now in opt) 2026-01-21 15:15:21 -08:00
Akash Levy b11037e6c6 Merge remote-tracking branch 'upstream/main' 2026-01-21 15:13:57 -08:00
Stan Lee f14eb4a7bb only check reg cells 2026-01-21 15:13:55 -08:00
Stan Lee 269b70c0f9 compiles 2026-01-21 12:32:38 -08:00
Stan Lee 0018037c16 minor changes 2026-01-21 12:25:28 -08:00
Stan Lee e824c8e0d6 ready for review 2026-01-21 09:00:46 -08:00
Stan Lee 31e32af4a8 greptile 2026-01-21 08:54:43 -08:00
Emil J 317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J 5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
Miodrag Milanović 2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy 
Avoid spurious copy in `IdStringCollector::trace_named()`
 2026-01-21 08:30:07 +01:00
Stan Lee d2e8f9b8a8 first round fixes 2026-01-20 21:45:13 -08:00
Robert O'Callahan 2c0448a81b Avoid spurious copy in `IdStringCollector::trace_named()` 2026-01-21 03:31:56 +00:00
github-actions[bot] 57ac113b7f Bump version 2026-01-21 00:27:51 +00:00
Stan Lee 29061d3051 leave no room for err 2026-01-20 15:55:05 -08:00
Stan Lee 45bd3f4515 change splitcells pass to remove some bracket from register names in blast mode 2026-01-20 15:50:43 -08:00
Stan Lee 60a81a2676 reg rename pass reads from vcd for original widths 2026-01-20 15:35:13 -08:00
Stan Lee a5106da733 line reduction 2026-01-20 11:56:57 -08:00
Stan Lee 0ea4bb8a2d comment 2026-01-20 11:55:54 -08:00
Stan Lee 80364c608e significantly cleaner 2026-01-20 11:29:56 -08:00
Miodrag Milanović bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017 
verific: add explicit System Verilog 2017 option
 2026-01-20 14:44:46 +01:00
Miodrag Milanovic d0fa4781c6 verific: Fix -sv2017 message and formatting 2026-01-20 08:07:26 +01:00
github-actions[bot] 49e5950791 Bump version 2026-01-20 00:26:10 +00:00
Stan Lee c471014878 slightly cleaner 2026-01-19 12:58:36 -08:00
Stan Lee 6303eed1b4 works hierarchy 2026-01-19 12:22:22 -08:00
Stan Lee 186fc15f8f passes simple test 2026-01-19 12:10:48 -08:00
Stan Lee e678e2a0c3 every step except wire connecting 2026-01-19 11:20:11 -08:00
Stan Lee 15026033a3 annotate original register width 2026-01-19 11:19:41 -08:00
Miodrag Milanovic cc3038f468 verific: Fix -sv2017 message 2026-01-19 16:32:46 +01:00
Miodrag Milanović 2bde91b6ef
Merge pull request #5618 from YosysHQ/update_abc 
Update ABC as per 2026-01-19
 2026-01-19 15:45:02 +01:00
nella 67d10a41e8
Merge pull request #5617 from YosysHQ/emil/consteval-description 
consteval: describe
 2026-01-19 14:56:24 +01:00
Miodrag Milanovic 691983be14 Update ABC as per 2026-01-19 2026-01-19 12:08:24 +01:00
Emil J 7880f31acb
Merge pull request #5531 from YosysHQ/emil/shuffle-contributing-docs 
docs: shuffle and expand contributing info
 2026-01-19 12:02:49 +01:00
Emil J. Tywoniak c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Emil J. Tywoniak befadf6d4d consteval: describe 2026-01-19 12:00:18 +01:00
Miodrag Milanović 9355fa5037
Merge pull request #5616 from rocallahan/fix-unused-var-warning 
Fix warning about unused variable in `dffunmap`.
 2026-01-19 08:24:48 +01:00
Robert O'Callahan 28c199fbbd Fix warning about unused variable in `dffunmap`. 2026-01-19 03:25:09 +00:00
Akash Levy 7792f0644a
Merge branch 'YosysHQ:main' into main 2026-01-18 17:17:45 -08:00
KrystalDelusion 8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err 
Improve error handling in sim
 2026-01-19 09:51:12 +13:00
Stan Lee 4a1af73ec0 activity pass and a vcd writer bug fix 2026-01-16 16:32:04 -08:00
Miodrag Milanovic d095d2c405 verific: add explicit System Verilog 2017 option 2026-01-16 07:56:53 +01:00
Natalia ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Akash Levy 33ddae41c3 Remove lut2bmux from silimate after upstreaming 2026-01-14 20:24:26 -08:00
Akash Levy ef98c62bf2 Merge 2026-01-14 18:34:16 -08:00
Natalia d5e1647d11 fix tests with truncation issues 2026-01-14 18:03:30 -08:00
github-actions[bot] 967b47d984 Bump version 2026-01-15 00:24:54 +00:00
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width 
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
 2026-01-14 14:58:53 -08:00
Natalia 60ac3670cb Fix truncation issue in opt_balance_tree pass 
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.

For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)

Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
 2026-01-14 13:14:56 -08:00