mirror of https://github.com/YosysHQ/yosys.git
significantly cleaner
This commit is contained in:
Stan Lee
parent
c471014878
commit
80364c608e
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@ -62,6 +62,7 @@ struct RegRenamePass : public Pass {
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// .*_reg[NUMBER] or .*_reg, can match NUMBER and part before _reg
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std::regex reg_regex("(.*)_reg(?:\\[(\\d+)\\])?$");
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for (auto module : design->selected_modules()) {
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pool<Wire *> wiresToRemove; // pool of wires to remove from the netlist
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for (auto cell : module->selected_cells()) {
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// Rename register output wires to corresponding testbench names
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@ -71,88 +72,64 @@ struct RegRenamePass : public Pass {
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// baseName is the part before _reg
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std::string baseName = match[1].str();
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std::string registerName = baseName;
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// Check if the register is a multi-bit register
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// Check if the register is a multi-bit register (look for [NUMBER] match in regex)
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bool isMultiBit = match.size() > 2 && match[2].matched;
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std::string indexStr;
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if (isMultiBit) {
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// indexStr is the NUMBER in .*_reg[NUMBER]
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indexStr = match[2].str();
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registerName += "_" + indexStr;
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}
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for (auto conn : cell->connections()) {
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if (conn.first == ID::Q && conn.second.is_wire()) {
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Wire *wire = conn.second.as_wire();
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Wire *oldWire = conn.second.as_wire();
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// Skip if this wire is a module port (input/output)
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if (wire->port_input || wire->port_output) {
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if (oldWire->port_input || oldWire->port_output) {
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log("Skipping port wire %s in register renaming for cell %s in module %s\n",
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wire->name.c_str(), log_id(cell), log_id(module));
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oldWire->name.c_str(), log_id(cell), log_id(module));
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continue;
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}
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// Skip if we already renamed the wire
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if (wire->name == registerName) {
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continue;
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}
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// Rename register
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log("Renaming register wire %s to %s for cell %s in module %s\n",
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wire->name.c_str(), registerName, log_id(cell), log_id(module));
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// Log relevant information for multi-bit registers for wire reconstruction
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// Different cases for multi-bit and single-bit registers
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if (isMultiBit) {
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std::string origRegWidth = cell->get_string_attribute("$ORIG_REG_WIDTH");
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auto key = std::make_pair(module, baseName);
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regWireMap[key].oldWires.push_back(std::make_pair(wire, std::stoi(indexStr)));
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regWireMap[key].origRegWidth = std::stoi(origRegWidth);
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}
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// Index of the register and original register width
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int index = std::stoi(match[2].str());
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int origRegWidth = std::stoi(cell->get_string_attribute("$ORIG_REG_WIDTH"));
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// Get or create the multi-bit wire
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Wire *newWire = module->wire(RTLIL::escape_id(baseName));
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if (newWire == nullptr) {
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// Wire doesn't exist, create it
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log("Creating multi-bit wire %s with width %d in module %s\n",
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baseName.c_str(), origRegWidth, log_id(module));
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newWire = module->addWire(RTLIL::escape_id(baseName), origRegWidth);
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}
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log("Connecting register wire %s to bit %d of %s in module %s\n",
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oldWire->name.c_str(), index, baseName.c_str(), log_id(module));
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module->rename(wire, registerName);
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count++;
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// Replace all uses of oldWire with newWire[index]
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auto rewriter = [&](SigSpec &sig) {
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sig.replace(SigBit(oldWire), SigSpec(newWire, index, 1));
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};
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module->rewrite_sigspecs(rewriter);
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// Mark old wire for deletion
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wiresToRemove.insert(oldWire);
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count++;
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} else {
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if (oldWire->name != baseName) {
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// Rename single-bit register to correct name from RTL
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log("Renaming register wire %s to %s for cell %s in module %s\n",
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oldWire->name.c_str(), baseName, log_id(cell), log_id(module));
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module->rename(oldWire, baseName);
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count++;
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}
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}
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}
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}
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}
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}
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}
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// Iterate over regWireMap to create new wires and connect renamed registers to it.
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// Only applies to multi-bit registers.
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for (const auto &[key, regWires] : regWireMap) {
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auto [mod, baseName] = key; // module and original register name in RTL
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// Create a new wire for the multi-bit register
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int width = regWires.origRegWidth;
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log("Creating new wire %s for register %s with width %d in module %s\n",
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baseName.c_str(), baseName.c_str(), width, log_id(mod));
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Wire *newWire = mod->addWire(baseName, width);
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// Initialize a pool of old wire to remove from the netlist
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pool<Wire *> oldWires;
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// Connect the renamed registers to the corresponding index of the new wire
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for (const auto &[oldWire, index] : regWires.oldWires) {
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// Get the old wire (the Q output that was renamed)
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log("Connecting renamed register %s to index %d of %s\n", oldWire->name.c_str(), index, baseName.c_str());
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// Connect the renamed register to the corresponding index of the new wiret
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mod->connect(SigSpec(newWire, index, 1), oldWire);
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// Replace all uses of oldWire with newWire[index] throughout the module
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auto rewriter = [&](SigSpec &sig) {
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sig.replace(SigBit(oldWire), SigSpec(newWire, index, 1));
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};
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mod->rewrite_sigspecs(rewriter);
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// Add the old wire to the list of old wires to delete
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oldWires.insert(oldWire);
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}
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// Delete the old wires
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mod->remove(oldWires);
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module->remove(wiresToRemove);
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}
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// End
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