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16785 Commits

Author SHA1 Message Date
Robert O'Callahan 9c51ba1b09 Reduce opt_clean parallelism 2026-03-06 02:20:16 +00:00
Robert O'Callahan 8d8c05b338 Fix `OptCleanPass` usage of `CleanRunContext` to avoid constructing extra `KeepCache` and `ParallelDispatchThreadPool` 2026-03-06 02:20:16 +00:00
Robert O'Callahan 32f5044eaf Clarify "Not passing module as function argument" comment 
This correct in terms of intent, it's just not fully enforced due to const laundering.
 2026-03-06 02:20:16 +00:00
Emil J. Tywoniak 70cc2d67fd opt_clean: refactor 2026-03-06 02:20:14 +00:00
Robert O'Callahan 1260fda83a Add 'init' attributes to RTLIL fuzzing 2026-03-06 02:20:08 +00:00
Robert O'Callahan cdfc586f18 Add unit tests for `ConcurrentWorkQueue` 2026-03-06 02:20:08 +00:00
Robert O'Callahan 1e96328ede Add some tests for `ShardedHashSet` 2026-03-06 02:20:08 +00:00
Robert O'Callahan 3910d569da Add unit tests for `ConcurrentQueue` and `ThreadPool` 2026-03-06 02:20:08 +00:00
Robert O'Callahan ac55935a68 Add unit-tests for `ParallelDispatchThread` and friends 2026-03-06 02:20:08 +00:00
Robert O'Callahan 3603cd52a0 Pass the module `Subpool` to `rmunused_module_signals` and parallelize that function 2026-03-06 02:20:08 +00:00
Robert O'Callahan 7f3b11e56b Add test that connects a wire with `init` to a constant 2026-03-06 02:20:08 +00:00
Robert O'Callahan 19a7c8fcf3 Pass the module `Subpool` to `rmunused_module_cells` and parallelize that function 2026-03-06 02:20:08 +00:00
Robert O'Callahan 8e044d1045 Pass the module `Subpool` to `rmunused_module_init` and parallelize that function 2026-03-06 02:20:06 +00:00
Robert O'Callahan a7437c636d Pass the toplevel thread pool to `rmunused_module`, create a `Subpool`, and parallelize `remove_temporary_cells` 2026-03-06 02:05:46 +00:00
Robert O'Callahan 887c32cb54 Create a toplevel `ParallelDispatchThreadPool` and parallelize `keep_cache_t::scan_module()` with it 2026-03-06 02:05:46 +00:00
Robert O'Callahan 72a21fe01d Introduce `RmStats` struct to encapsulate removal statistics 
Turns out this is not strictly necessary for this PR but it's
still a good thing to do and makes it clearer that the stats
are not modified in a possibly racy way.
 2026-03-06 02:05:43 +00:00
Robert O'Callahan c2bb7d6a82 Make `keep_cache_t` process all modules up-front instead of on-demand 
We will want to query `keep_cache` from parallel threads. If we compute
the results on-demand, that means we need synchronization for cache
access in those queries, which adds complexity and overhead. Instead, prefill
the cache with the status of all relevant modules. Note that this doesn't
actually do more work --- we always consult `keep_cache` for all cells of
all selected modules, so scanning all those cells and determining the kept
status of all dependency modules is always required.

Later in this PR we're going to parallelize `scan_module` itself, and that's also
much easier to do when no other parallel threads are running.
 2026-03-06 02:05:04 +00:00
Robert O'Callahan b42bb05b63 Parallelize `Design::check()` 2026-03-06 02:03:21 +00:00
Robert O'Callahan e2166c4684 Parallelize `collect_garbage()` 2026-03-06 02:03:21 +00:00
Robert O'Callahan 5ff7d344c9 Add `FfInitVals::set_parallel()` method 
We'll use this later in the PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan fe329a0e14 Add `MonotonicFlag` 
We'll use this later in the PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan e71da96314 Add `ConcurrentWorkQueue` 
We'll use this later in the PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan ab238c3145 Add `ShardedHashSet` 
We'll use this later in the PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan 87521df534 Add `ShardedVector` 
We'll use this later in the PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan b079e5721c Add `ParallelDispatchThreadPool` 
We'll use this later in the PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan 898a288a99 Add `work_pool_size`, `IntRange`, `item_range_for_worker`, and `ThreadIndex` 
We'll use these later in this PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan 13d9fffdb9 Work around `std::reverse` miscompilation with empty range 
This causes problems when compiling with fuzzing instrumenation enabled.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan bd7f2d9ba4 Make `log_error()` work in a `Multithreaded` context. 
`log_error()` causes an exit so we don't have to try too hard here. The main
thing is to ensure that we normally are able to exit without causing a stack
overflow due to recursive asserts about not being in a `Multithreaded` context.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan 7af5dbae35 Add `IdString::unescape()` method 
We've already talked about adding this as an alternative to `log_id()`, and we'll
need it later in this PR.
 2026-03-06 02:03:21 +00:00
Miodrag Milanović 95d738edc0
Merge pull request #5726 from YosysHQ/emil/double-expose-yosys_celltypes 
celltypes: include newcelltypes to allow legacy code access to migrat…
 2026-03-05 11:36:36 +00:00
Emil J 629bf3dffd
Merge pull request #5630 from apullin/array-assignment 
ast: Add support for array-to-array assignment
 2026-03-05 11:10:12 +00:00
Emil J. Tywoniak 23eb38fe3f celltypes: include newcelltypes to allow legacy code access to migrated yosys_celltypes 2026-03-05 11:59:20 +01:00
Lofty 4caffa7ebd
Merge pull request #5725 from yrabbit/disable-wm-2 
GOWIN. Disable read-before-write mode.
 2026-03-05 05:36:28 +00:00
Andrew Pullin 6ac8c8cb05 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-03-04 21:34:40 -08:00
YRabbit 26dc01102e GOWIN. Disable read-before-write mode. 
According to the latest documentation from GOWIN -
"UG285-1.4E Gowin BSRAM & SSRAM User Guide"

The dual port BSRAM of all 55nm devices (including GW1N, GW2A and GW1A
series) does not support the read-before-write mode (WRITE_MODE = 2)

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2026-03-05 09:17:37 +10:00
Emil J 0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
Emil J. Tywoniak 6485a13809 newcelltypes: mark header unstable 2026-03-04 15:17:26 +01:00
Miodrag Milanović 3bc26ff4d0
Merge pull request #5723 from YosysHQ/micko/merge_queue 
CI: add support for merge queue
 2026-03-04 13:18:09 +01:00
nella 16b1a914f1 Aiger use defines for known ops. 2026-03-04 12:39:45 +01:00
nella 04822c6660 Readd builtin_ff_cell_types for plugin parity. 2026-03-04 12:39:45 +01:00
nella b8ee0803ab Remove todo. 2026-03-04 12:39:45 +01:00
nella 66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
nella cae54a4c7b Aiger use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak 6d4736269b newcelltypes: extend testing 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak 0284595e9c celltypes: fix absurd eval declarations 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak 793a3513c6 newcelltypes: use unordered_map 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak ae10e9e955 pyosys: disable test 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak 661fcb24cb newcelltypes: fix MSVC build 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak f594014bef newcelltypes: proper bounds for unit test 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak 12412d1fa5 register: use newcelltypes 2026-03-04 12:39:45 +01:00