luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
17,402 Commits 133 Branches 69 Tags 66 MiB
Commit Graph

527 Commits

Author SHA1 Message Date
Akash Levy 950c619569 Smallfixes 2025-11-11 23:50:04 -08:00
Akash Levy e21324d609 Merge from upstream 2025-11-11 22:52:11 -08:00
Robert O'Callahan 1cf3497d15 Repack SigSpecs when possible 2025-11-07 15:54:56 +00:00
Robert O'Callahan 38d1d071a5 Implement SigSpec::updhash() using a relaxed atomic for thread-safety 2025-11-07 15:54:56 +00:00
Robert O'Callahan 745222fa3b Make SigSpec::unpack() non-const 2025-11-07 15:54:56 +00:00
Robert O'Callahan 870ae18a2d Switch the SigSpec packed representation to allow just a single chunk that's inline in the SigSpec. 
Single-chunk SigSpecs are very common and this avoids a heap allocation. It also simplifies
some algorithms.
 2025-11-07 15:54:56 +00:00
Robert O'Callahan e1169d03fe Use chunks iterator for SigSpec::extract() 2025-11-07 15:54:56 +00:00
Robert O'Callahan 4939484840 Don't reset the hash when unpacking, instead clear the hash whenever bits are modified 2025-11-07 15:54:56 +00:00
Robert O'Callahan aa4a0fe815 Use size() instead of direct access to width_ in many places 2025-11-07 15:54:56 +00:00
Robert O'Callahan 619f49eabe Remove unnecessary pack() from SigSpec::extend_u0() 2025-11-07 15:54:55 +00:00
Robert O'Callahan b612c1bb39 Simplify SigSpec::as_bit() 2025-11-07 15:54:55 +00:00
Robert O'Callahan a69d48dd19 Instead of using packing and hashing to compute SigSpec ordering and equality, just use the width and chunkwise comparisons 
This avoids having to pack and compute hashes, and generally results in a
simpler ordering.
 2025-11-07 15:54:55 +00:00
Robert O'Callahan 7394a2c597 Make SigSpec conversion to vector of SigChunk use chunks iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 974b4dbe25 Make SigSpec::parse_rhs use is_chunk to avoid direct access to chunks_ 2025-11-07 15:54:55 +00:00
Robert O'Callahan 62cd3ddfb8 Make SigSpec::to_sigbit_pool use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 4ed25c0538 Make SigSpec::to_sigbit_set use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 39b89aae88 Use SigSpec::try_as_const in some places 2025-11-07 15:54:55 +00:00
Robert O'Callahan dd3940c8bb Make SigSpec::is_one_hot use try_as_const 2025-11-07 15:54:55 +00:00
Robert O'Callahan ce597dc38c Fix try_as_const/as_wire/as_chunk 2025-11-07 15:54:55 +00:00
Robert O'Callahan 0281ed1458 Add try_as_const and use the const iterator a bit more 2025-11-07 15:54:55 +00:00
Robert O'Callahan 0091d14e6d Make SigSpec::has_marked_bits use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 80b3efb3da Make SigSpec::has_const(State) use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan ed8022f53f Make SigSpec::has_const use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 1893c61fe2 Make SigSpec::is_fully_undef use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan e2defe7898 Make SigSpec::is_fully_def use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 152a487cc8 Make SigSpec::is_fully_ones use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan ddd04e13e0 Make SigSpec::is_fully_zero use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan a7ac396fd9 Make is_fully_const use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan b0ee67a355 Make SigSpec::is_wire/is_chunk/is_fully_const use chunk iterator 2025-11-07 15:54:54 +00:00
Robert O'Callahan fc7d61132d Make SigSpec::updhash() use chunk iterator 2025-11-07 15:54:54 +00:00
Robert O'Callahan 3f7af10eda Make SigSpec::chunks() return an object that can be iterated over without packing the SigSpec 2025-11-07 15:54:54 +00:00
Robert O'Callahan 8d4f790951 Make Module stop accessing internals of SigSpec 2025-11-07 13:25:38 +00:00
Mohamed Gaber dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11 2025-10-26 02:39:43 +03:00
Mohamed Gaber d6b9158fa3
pyosys: fix regressions from 0.58 
- consistently use value semantics for objects passed along FFI boundary
  (not ideal but matches previous behavior)
- add new overload of RTLIL::Module: addMemory that does not require a "donor" object
  - the idea is `Module`, `Memory`, `Wire`, `Cell` and `Process` cannot be directly constructed in Python and can only be added to the existing memory hierarchy in `Design` using the `add` methods - `Memory` requiring a donor object was the odd one out here
- fix superclass member wrapping only looking at direct superclass for inheritance instead of recursively checking superclasses
- fix superclass member wrapping not using superclass's denylists
- fix Design's `__str__` function not returning a string
- fix the generator crashing if there's any `std::function` in a header
- misc: add a crude `__repr__` based on `__str__`
 2025-10-26 02:21:40 +03:00
Emil J a80462f27f
Merge pull request #5339 from rocallahan/fast-rtlil-parser 
Rewrite the RTLIL parser for efficiency
 2025-10-08 14:52:37 +02:00
Mohamed Gaber 447a6cb3f0
misc: `WITH_PYTHON` -> `YOSYS_ENABLE_PYTHON` 
For consistency.

Also trying a new thing: only rebuilding objects that use the pybind11 library. The idea is these are the only objects that include the Python/pybind headers and thus the only ones that depend on the Python ABI in any capacity, so other objects can be reused across wheel builds. This has the potential to cut down build times.
 2025-10-03 11:54:44 +03:00
Robert O'Callahan db3d9a1baf When adding named elements to an RTLIL::Module, std::move the name to avoid refcount churn 2025-09-30 21:39:18 +00:00
Robert O'Callahan 6b43fca8df Make the Const string constructor take the string by value and move it into the const 2025-09-30 21:39:18 +00:00
Akash Levy 16215b8786 Merge upstream 2025-09-29 20:58:56 -07:00
Akash Levy 93a24fe275 Put back is_mostly_const 2025-09-29 20:56:58 -07:00
Akash Levy fbc2b71ed4 Revert some stuff 2025-09-29 00:43:49 -07:00
Jannis Harder 86fb2f16f7 bufnorm: Refactor and fix incremental bufNormalize 
This fixes some edge cases the previous version didn't handle properly
by simplifying the logic of determining directly driven wires and
representatives to use as buffer inputs.
 2025-09-29 08:21:28 +02:00
Akash Levy 652a9a63b2 Update to latest and fix all disabled tests 2025-09-28 01:33:08 -07:00
Jannis Harder 9c1d0a2346
Merge pull request #5382 from rocallahan/fix-bounds-check 
Fix off-by-one error in bounds check in `RTLIL::SigChunk::operator[]`
 2025-09-24 08:41:16 +02:00
Robert O'Callahan 0a17205a95 Fix off-by-one error in bounds check 2025-09-23 21:29:57 +00:00
Akash Levy ab006776d0 Bump 2025-09-23 00:40:20 -07:00
Robert O'Callahan effc52fedc Make `ID::` constants be `StaticIdString`s for better optimization. 
Their internal indexes will be known at compile time, like we already support for the `ID()` macro.
 2025-09-23 03:25:16 +00:00
Akash Levy d16ca47549
Merge branch 'YosysHQ:main' into main 2025-09-22 17:47:23 -07:00
Emil J a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 
write_rtlil: don't sort
 2025-09-22 11:14:39 +02:00
Akash Levy 503b0aae20 Use long long int for pyosys 2025-09-21 02:20:13 -07:00