Revert some stuff

.github/workflows/test-build.yml

@@ -261,7 +261,7 @@ jobs:
       - name: Run tests
         shell: bash
         run: |
-          make -C docs test -j${{ env.procs }} SMALL=0 ENABLE_PLUGINS=1 ENABLE_PYOSYS=0 ENABLE_CCACHE=0 ENABLE_EDITLINE=0
+          make -C docs test -j$procs SMALL=0 ENABLE_PLUGINS=1 ENABLE_PYOSYS=0 ENABLE_CCACHE=0 ENABLE_EDITLINE=0
 
   test-docs-build:
     name: Try build docs

.github/workflows/test-sanitizers.yml

@@ -98,7 +98,7 @@ jobs:
         run: |
           make config-$CC SMALL=0 ENABLE_PLUGINS=1 ENABLE_PYOSYS=0 ENABLE_CCACHE=0 ENABLE_EDITLINE=0 ENABLE_VERIFIC=0
           echo 'SANITIZER = ${{ matrix.sanitizer }}' >> Makefile.conf
-          make -j$procs ENABLE_LTO=1 SMALL=0 ENABLE_PLUGINS=1 ENABLE_PYOSYS=0 ENABLE_CCACHE=0 ENABLE_EDITLINE=0 ENABLE_VERIFIC=0
+          make -j$procs SMALL=0 ENABLE_PLUGINS=1 ENABLE_PYOSYS=0 ENABLE_CCACHE=0 ENABLE_EDITLINE=0 ENABLE_VERIFIC=0
 
       - name: Log yosys-config output
         run: |
@@ -107,7 +107,7 @@ jobs:
       - name: Run tests
         shell: bash
         run: |
-          make -j$procs test TARGETS= EXTRA_TARGETS= CONFIG=$CC SMALL=0 ENABLE_PLUGINS=1 ENABLE_PYOSYS=0 ENABLE_CCACHE=0 ENABLE_EDITLINE=0 ENABLE_VERIFIC=0
+          make -j$procs test TARGETS= EXTRA_TARGETS= SMALL=0 ENABLE_PLUGINS=1 ENABLE_PYOSYS=0 ENABLE_CCACHE=0 ENABLE_EDITLINE=0 ENABLE_VERIFIC=0
 
       - name: Report errors
         if: ${{ failure() }}

.vscode/settings.json

@@ -72,6 +72,5 @@
     "algorithm": "cpp",
     "*.inc": "cpp",
     "tuple": "cpp"
-  },
-  "cmake.sourceDirectory": "/Users/akashlevy/Documents/preqorsor/third_party/yosys/abc"
+  }
 }

kernel/cost.cc

@@ -102,13 +102,6 @@ static bool is_free(RTLIL::IdString type)
 	  type.in(ID($specrule), ID($specify2), ID($specify3)));
 }
 
-static bool is_mem(RTLIL::IdString type)
-{
-	return (
-		// tags
-		type.in(ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2)));
-}
-
 unsigned int max_inp_width(RTLIL::Cell *cell)
 {
 	unsigned int max = 0;
@@ -213,13 +206,9 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
 	} else if (is_free(cell->type)) {
 		log_debug("%s is free\n", cell->name);
 		return 0;
-	} else if (is_mem(cell->type)) {
-		// SILIMATE: Memory cells have no bearing on cross module optimizations
-		log_debug("%s is mem\n", cell->name.c_str());
-		return 1;
 	}
 	// TODO: $fsm
-	// ignored: $pow
+	// ignored: $pow $memrd $memwr $meminit (and v2 counterparts)
 
 	log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
 	return 1;

kernel/modtools.h

@@ -78,7 +78,6 @@ struct ModIndex : public RTLIL::Monitor
 	SigMap sigmap;
 	RTLIL::Module *module;
 	std::map<RTLIL::SigBit, SigBitInfo> database;
-	int reload_counter;
 	int auto_reload_counter;
 	bool auto_reload_module;
 
@@ -107,10 +106,6 @@ struct ModIndex : public RTLIL::Monitor
 
 	void reload_module(bool reset_sigmap = true)
 	{
-		reload_counter++;
-		if (reload_counter % 10 == 0)
-			log_warning("ModIndex::reload_module() called %d times.\n", reload_counter);
-
 		if (reset_sigmap) {
 			sigmap.clear();
 			sigmap.set(module);
@@ -236,7 +231,6 @@ struct ModIndex : public RTLIL::Monitor
 
 	ModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)
 	{
-		reload_counter = 0;
 		auto_reload_counter = 0;
 		auto_reload_module = true;
 		module->monitors.insert(this);

kernel/rtlil.cc

@@ -5437,18 +5437,6 @@ bool RTLIL::SigSpec::is_chunk() const
 	return GetSize(chunks_) == 1;
 }
 
-bool RTLIL::SigSpec::is_mostly_const() const
-{
-	cover("kernel.rtlil.sigspec.is_mostly_const");
-
-	pack();
-	int constbits = 0;
-	for (auto it = chunks_.begin(); it != chunks_.end(); it++)
-		if (it->width > 0 && it->wire == NULL)
-			constbits += it->width;
-	return (constbits > width_/2);
-}
-
 bool RTLIL::SigSpec::known_driver() const
 {
 	pack();

kernel/rtlil.h

@@ -1346,8 +1346,6 @@ public:
 	bool is_chunk() const;
 	inline bool is_bit() const { return width_ == 1; }
 
-	bool is_mostly_const() const;
-
 	bool known_driver() const;
 
 	bool is_fully_const() const;

passes/hierarchy/keep_hierarchy.cc

@@ -42,9 +42,7 @@ struct ThresholdHierarchyKeeping {
 			return 0;
 
 		if (module->get_blackbox_attribute())
-			// SILIMATE: Blackboxes have no bearing on cross module optimizations
-			// log_error("Missing cost information on instanced blackbox %s\n", log_id(module));
-			return 1;
+			log_error("Missing cost information on instanced blackbox %s\n", log_id(module));
 
 		if (done.count(module))
 			return done.at(module);

tests/arch/microchip/widemux.ys

@@ -25,8 +25,8 @@ module widemux(
 endmodule
 EOT
 synth_microchip -top widemux -family polarfire -noiopad
-select -assert-count 3 t:CFG3
-select -assert-none t:CFG3 %% t:* %D
+select -assert-count 1 t:MX4
+select -assert-none t:MX4 %% t:* %D
 
 # RTL style is different here forming a different structure
 read_verilog ../common/mux.v