luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Make SigSpec::is_fully_zero use chunk iterator

This commit is contained in:
Robert O'Callahan 2025-10-28 12:36:47 +00:00
parent a7ac396fd9
commit ddd04e13e0
1 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
kernel/rtlil.cc
View File

@ -5450,12 +5450,11 @@ bool RTLIL::SigSpec::is_fully_zero() const
{
cover("kernel.rtlil.sigspec.is_fully_zero");
pack();
for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
if (it->width > 0 && it->wire != NULL)
for (auto &chunk : chunks()) {
if (chunk.width > 0 && chunk.wire != NULL)
return false;
for (size_t i = 0; i < it->data.size(); i++)
if (it->data[i] != RTLIL::State::S0)
for (RTLIL::State d : chunk.data)
if (d != RTLIL::State::S0)
return false;
}
return true;