Commit Graph

744 Commits

Author SHA1 Message Date
Robert O'Callahan 8d8c05b338 Fix `OptCleanPass` usage of `CleanRunContext` to avoid constructing extra `KeepCache` and `ParallelDispatchThreadPool` 2026-03-06 02:20:16 +00:00
Robert O'Callahan 32f5044eaf Clarify "Not passing module as function argument" comment
This correct in terms of intent, it's just not fully enforced due to const laundering.
2026-03-06 02:20:16 +00:00
Emil J. Tywoniak 70cc2d67fd opt_clean: refactor 2026-03-06 02:20:14 +00:00
Robert O'Callahan 3603cd52a0 Pass the module `Subpool` to `rmunused_module_signals` and parallelize that function 2026-03-06 02:20:08 +00:00
Robert O'Callahan 19a7c8fcf3 Pass the module `Subpool` to `rmunused_module_cells` and parallelize that function 2026-03-06 02:20:08 +00:00
Robert O'Callahan 8e044d1045 Pass the module `Subpool` to `rmunused_module_init` and parallelize that function 2026-03-06 02:20:06 +00:00
Robert O'Callahan a7437c636d Pass the toplevel thread pool to `rmunused_module`, create a `Subpool`, and parallelize `remove_temporary_cells` 2026-03-06 02:05:46 +00:00
Robert O'Callahan 887c32cb54 Create a toplevel `ParallelDispatchThreadPool` and parallelize `keep_cache_t::scan_module()` with it 2026-03-06 02:05:46 +00:00
Robert O'Callahan 72a21fe01d Introduce `RmStats` struct to encapsulate removal statistics
Turns out this is not strictly necessary for this PR but it's
still a good thing to do and makes it clearer that the stats
are not modified in a possibly racy way.
2026-03-06 02:05:43 +00:00
Robert O'Callahan c2bb7d6a82 Make `keep_cache_t` process all modules up-front instead of on-demand
We will want to query `keep_cache` from parallel threads. If we compute
the results on-demand, that means we need synchronization for cache
access in those queries, which adds complexity and overhead. Instead, prefill
the cache with the status of all relevant modules. Note that this doesn't
actually do more work --- we always consult `keep_cache` for all cells of
all selected modules, so scanning all those cells and determining the kept
status of all dependency modules is always required.

Later in this PR we're going to parallelize `scan_module` itself, and that's also
much easier to do when no other parallel threads are running.
2026-03-06 02:05:04 +00:00
Emil J. Tywoniak 07ec8708e4 share: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 9e59f05c25 newcelltypes: wrap design celltypes support 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 35ccaa60d7 newcelltypes: TurboCellTypes -> StaticCellTypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 6adc08b0e5 opt_expr: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 3671d577a0 opt_clean: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J 1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift
opt_expr: fix const lhs of $pow to $shl
2026-02-05 13:09:01 +01:00
Emil J 8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals
Clean up `compare_signals()` in `opt_clean`
2026-02-04 17:45:05 +01:00
Emil J 992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort
Remove `Design::sort()` calls from optimization passes
2026-02-04 16:55:56 +01:00
Emil J. Tywoniak 3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
nella 8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite
opt_dff restructure.
2026-01-28 14:41:40 +01:00
nella 9367090763 OptDff more accurate ctrl/pattern desc. 2026-01-26 22:19:36 +01:00
nella 5803461c24 opt_dff pattern extraction. 2026-01-26 22:10:10 +01:00
nella 8576055dea Fix tests. 2026-01-26 18:41:41 +01:00
nella a75e0b2e92 opt_dff minor cleanup, added tests for comp var. 2026-01-26 14:24:01 +01:00
Robert O'Callahan 32e96605d4 Don't update `used_signals` for retained wires in `rmunused_module_signals`.
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
2026-01-24 03:41:18 +00:00
Robert O'Callahan 7d53d64a47 Make the call to `compare_signals()` easier to read.
The negation here is confusing. The intent of the code is "if `s1` is preferred
over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit`
in `assign_map`", so write the code that way instead of "if `s2` is not preferred
over `s1` ...".

This doesn't change any behavior now that `compare_signals()` is a total order,
i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal.
Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's
already a noop in that case.
2026-01-24 02:01:05 +00:00
Robert O'Callahan 2468b391bf Make `compare_signals` produce a total order.
Currently when `s1` and `s2` are different bits of the same wire,
it is possible for both `compare_signals(s1, s2)` and `compare_signals(s2, s1)` to
return false. This means the calling code will call `assign_map.add()` for
both `s1` and `s2`, which doesn't make much sense --- one of `s1` or `s2`
should be consistently preferred.

So fix that by preferring the `SigBit` with the smaller bit offset.
2026-01-24 02:00:33 +00:00
nella 0e4282d442 Add more opt_dff documentation. 2026-01-23 09:17:14 +01:00
Robert O'Callahan e87bb65956 Move `Design::sort()` calls out of `opt` and `opt_clean` passes into the synth passes that need them. 2026-01-23 01:14:35 +00:00
nella f6eba53d1f Fix copyright header. 2026-01-21 14:52:19 +01:00
nella 2c12545cf3 opt_dff restructure. 2026-01-21 10:08:44 +01:00
Emil J. Tywoniak c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
2026-01-14 14:58:53 -08:00
Natalia 60ac3670cb Fix truncation issue in opt_balance_tree pass
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.

For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)

Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
2026-01-14 13:14:56 -08:00
Natalia Kokoromyti 6aef8ea8ab Add missing <deque> include for MSVC compatibility 2026-01-13 15:31:46 -08:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
2026-01-13 14:20:11 -08:00
Emil J. Tywoniak 8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Robert O'Callahan 8da919587d Parallelize `opt_merge`.
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
2026-01-08 04:21:39 +00:00
Emil J 5c630a366d
Merge pull request #5555 from rocallahan/defer-redirects
Defer redirecting cell outputs when merging cells in `opt_merge` untill after we've done a full pass over the cells.
2026-01-06 18:48:16 +01:00
Robert O'Callahan 042ec1cf60 Defer redirecting cell outputs when merging cells in `opt_merge` until after we've done a full pass over the cells.
This avoids changing `assign_map` and `initvals`, which are inputs to the hash function for `known_cells`,
while `known_cells` exists. Changing the hash function for a hashtable while it exists leads to
confusing behavior. That also means the exact behavior of `opt_merge` cannot be reproduced by a
parallel implementation.
2026-01-06 16:21:48 +00:00
N. Engelhardt 45d654e2d7 avoid merging formal properties 2025-12-17 20:25:24 +01:00
Robert O'Callahan 638e904f91 Remove cover() coverage tracking 2025-12-04 16:27:13 +01:00
Robert O'Callahan 325b27f43a Avoid calling IdString::c_str() in opt_clean 2025-11-12 11:52:04 +01:00
Robert O'Callahan 54bde15329 Implement IdString garbage collection instead of refcounting. 2025-11-12 11:52:04 +01:00
Emil J 7719beb4ae
Merge pull request #5349 from rocallahan/cleanup-hashops
Reduce hashops verbiage in `OptMergePass`
2025-09-30 19:34:44 +02:00
Jannis Harder 47639f8a98
Merge pull request #5388 from jix/bufnorm-followup
Refactor and fixes to incremental bufNormalize + related changes
2025-09-29 15:15:29 +02:00
Emil J 87c1a868d3
Merge pull request #5384 from rocallahan/simplify-opt-merge-logic
Move `OptMerge` cell filtering logic to happen while building the cell vector
2025-09-29 15:03:01 +02:00
Martin Povišer a9318db2fa opt_hier: Adjust messages 2025-09-29 12:27:27 +02:00
Martin Povišer ffe2f7a16d opt_hier: Fix two optimizations conflicting
Fix a conflict between the following two:

 * propagation of tied-together inputs in
 * propagation of unused inputs out
2025-09-29 12:27:27 +02:00
Jannis Harder cbc1055517 opt_clean: Fix debug output when cleaning up bufnorm cells 2025-09-29 08:21:28 +02:00