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16608 Commits

Author SHA1 Message Date
Akash Levy 3733ad3879
Merge branch 'YosysHQ:main' into main 2025-08-11 09:26:32 -07:00
Jannis Harder 2d90e80b52
Merge pull request #5270 from zhanghongce/main 
Reorder the port wire declarations to follow the same order of the port declarations
 2025-08-11 15:35:25 +02:00
Akash Levy d0ab898e88
Merge branch 'YosysHQ:main' into main 2025-08-10 22:46:15 -07:00
Miodrag Milanović 8c71226d00
Merge pull request #5276 from YosysHQ/krys/bump_nix 
Bump nix on CI
 2025-08-09 07:12:22 +02:00
github-actions[bot] 0d4585dd5f Bump version 2025-08-09 00:24:43 +00:00
KrystalDelusion 6c84c4a4fc
extra-builds.yml: Bump nix 2025-08-09 11:19:24 +12:00
KrystalDelusion 1ae82d7b9d
Merge pull request #5233 from YosysHQ/krys/equiv_assume 
Assumptions for equiv_*
 2025-08-09 10:39:04 +12:00
Akash Levy 0354098c08
Merge pull request #84 from neildeo05/sim_and_clockgate 
add clockgate to makefile, add Density to sim pass
 2025-08-08 11:08:41 -07:00
Neil Deo 1122b92247 Use hardtabs 2025-08-08 11:08:20 -07:00
Neil Deo 07b54dff2b fix bad indentation 2025-08-08 10:39:25 -07:00
Akash Levy 613dfcc6b4
Merge branch 'YosysHQ:main' into main 2025-08-08 10:37:08 -07:00
Emil J d68d28d05e
Merge pull request #5183 from YosysHQ/emil/test-diagnostics 
logger: add -expect types prefix-log, prefix-warning, prefix-error
 2025-08-08 14:46:25 +02:00
Akash Levy 7a055dbe32 Use restricted multiport RAMs in Verific 2025-08-08 02:44:24 -07:00
Emil J 94d3b3eb5a
Merge pull request #5273 from YosysHQ/emil/krys-equiv_assume-refactor 
equiv_simple: refactor
 2025-08-08 10:52:15 +02:00
Hongce Zhang 76e507f307 update verilog_backend according to Github comments 2025-08-08 16:17:37 +08:00
Akash Levy 3311056d81 Revert "Revert some vhdl stuff" 
This reverts commit 6a9102346a.
 2025-08-08 01:16:49 -07:00
Akash Levy 6a9102346a Revert some vhdl stuff 2025-08-08 01:05:57 -07:00
Akash Levy 0e50fd3b74 Restricted multiport 2025-08-08 00:37:20 -07:00
Akash Levy 61bac59238 Update Verific to handle large memories better 2025-08-07 19:38:30 -07:00
Neil Deo 88816e390e add clockgate to makefile, add Density to sim pass 2025-08-07 18:07:15 -07:00
Akash Levy c4b20f14ea
Merge branch 'YosysHQ:main' into main 2025-08-07 17:58:29 -07:00
Krystine Sherwin e02f4469c0
equiv_simple: Avoid std::array 
VS build currently failing with `error C2641: cannot deduce template arguments for 'std::array'`.
Changing to `std::array<Cone, 2>` gives `error C2027: use of undefined type` instead.
 2025-08-08 12:37:38 +12:00
github-actions[bot] c9558b3d4f Bump version 2025-08-08 00:26:50 +00:00
Akash Levy 77be4d7be7 Bump Yosys to latest 2025-08-07 17:22:25 -07:00
Emil J. Tywoniak fcd9f98245 equiv_simple: refactor 2025-08-08 01:35:33 +02:00
KrystalDelusion 7f0e864d44
Merge pull request #5265 from bhagwat-rahul/fix-package-import 
Support package import
 2025-08-08 09:32:54 +12:00
Emil J 21b9c8e4c6
Merge pull request #5236 from rocallahan/const-lookup 
Make `dict` and `pool` const lookup methods never rehash the hashtable
 2025-08-07 11:43:39 +02:00
Emil J 1e58443397
Merge pull request #5264 from YosysHQ/krys/raise_error_always 
raise_error: Add -always
 2025-08-07 11:43:04 +02:00
Miodrag Milanovic e6059d042d Next dev cycle 2025-08-07 09:20:45 +02:00
Miodrag Milanovic 9c447ad9d4 Release version 0.56 2025-08-07 07:59:29 +02:00
Hongce Zhang b635ab72bf Merge branch 'main' of github.com:zhanghongce/yosys 2025-08-07 11:37:55 +08:00
Hongce Zhang 3cbbb9456d reorder verilog backend port wires 2025-08-07 11:37:23 +08:00
github-actions[bot] ab66d8b814 Bump version 2025-08-07 00:27:08 +00:00
KrystalDelusion 4230c2712f
Merge pull request #5269 from georgerennie/george/pyosys_source_location 
pyosys: support trailing defaulted source_location arguments
 2025-08-07 11:50:06 +12:00
Rahul Bhagwat 5cc1365b32
add newline - whitespace 2025-08-06 19:00:11 -04:00
Lofty 2298a2aa86
Merge pull request #4750 from georgerennie/george/pyosys_dereference 
pyosys: dereference cpp objects when constructing a tuple
 2025-08-06 22:03:03 +01:00
George Rennie 46a711d566 py_wrap_generator.py: support srd::source_location as trailing default argument 2025-08-06 21:38:03 +01:00
George Rennie b610afbc1b py_wrap_generator.py: whitespace 2025-08-06 21:37:28 +01:00
George Rennie 96108ad8b4 kernel/register.h: whitespace 2025-08-06 21:34:37 +01:00
Rahul Bhagwat f12055d3e0
rm debug logs 2025-08-06 15:39:36 -04:00
Rahul Bhagwat d3c8e6c14c
use more standard naming conventions 2025-08-06 15:39:30 -04:00
Rahul Bhagwat 7e0157ba2b
fix whitespace issues 2025-08-06 15:32:36 -04:00
Emil J 8576d2d147
Merge pull request #5263 from rocallahan/stringf-width 
Making `stringf()` use the format conversion specs as-is without widening them
 2025-08-06 11:36:28 +02:00
KrystalDelusion bc0f70563a
Merge pull request #5255 from YosysHQ/krys/re-cmdref 
Reapply "Add groups to command reference"
 2025-08-06 15:25:03 +12:00
Krystine Sherwin b1eeb7de3d
Less verbose equiv assumes 
both only print on the first step, and equiv_simple only prints if also verbose
 2025-08-06 15:21:10 +12:00
Krystine Sherwin f9e8127e2b
tests: Add equiv_induct to equiv_assume.ys 2025-08-06 15:13:04 +12:00
Krystine Sherwin 93b39ad9b3
equiv_induct: Add -set-assumes option 
Uses mostly the same code as equiv_simple, but the assumes are already being imported so long as they're in the selection, so it's even easier.
 2025-08-06 15:12:48 +12:00
Krystine Sherwin 20a51742f4
Docs: Fix cmd links from bugpoint docs 2025-08-06 13:52:13 +12:00
Krystine Sherwin ab403635e3
CI: Enable source tracking for reusable build 
The `test-docs-build` jobs require source tracking enabled to prevent warnings-as-errors.
Also add an extra note to the readme in case users run into the same.
 2025-08-06 13:52:13 +12:00
Krystine Sherwin 891a907a30
Add and use ENABLE_HELP_SOURCE 
Conditionally include help source tracking to preserve ABI.
Docs builds can (and should) use `ENABLE_HELP_SOURCE` so that the generated sphinx docs can perform default grouping and link to source files.
Regular user-builds don't need the source tracking.
 2025-08-06 13:52:13 +12:00