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572 Commits

Author SHA1 Message Date
Robert O'Callahan 870ae18a2d Switch the SigSpec packed representation to allow just a single chunk that's inline in the SigSpec. 
Single-chunk SigSpecs are very common and this avoids a heap allocation. It also simplifies
some algorithms.
 2025-11-07 15:54:56 +00:00
Robert O'Callahan e1169d03fe Use chunks iterator for SigSpec::extract() 2025-11-07 15:54:56 +00:00
Robert O'Callahan 4939484840 Don't reset the hash when unpacking, instead clear the hash whenever bits are modified 2025-11-07 15:54:56 +00:00
Robert O'Callahan aa4a0fe815 Use size() instead of direct access to width_ in many places 2025-11-07 15:54:56 +00:00
Robert O'Callahan 619f49eabe Remove unnecessary pack() from SigSpec::extend_u0() 2025-11-07 15:54:55 +00:00
Robert O'Callahan b612c1bb39 Simplify SigSpec::as_bit() 2025-11-07 15:54:55 +00:00
Robert O'Callahan a69d48dd19 Instead of using packing and hashing to compute SigSpec ordering and equality, just use the width and chunkwise comparisons 
This avoids having to pack and compute hashes, and generally results in a
simpler ordering.
 2025-11-07 15:54:55 +00:00
Robert O'Callahan 7394a2c597 Make SigSpec conversion to vector of SigChunk use chunks iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 974b4dbe25 Make SigSpec::parse_rhs use is_chunk to avoid direct access to chunks_ 2025-11-07 15:54:55 +00:00
Robert O'Callahan 62cd3ddfb8 Make SigSpec::to_sigbit_pool use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 4ed25c0538 Make SigSpec::to_sigbit_set use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 39b89aae88 Use SigSpec::try_as_const in some places 2025-11-07 15:54:55 +00:00
Robert O'Callahan dd3940c8bb Make SigSpec::is_one_hot use try_as_const 2025-11-07 15:54:55 +00:00
Robert O'Callahan ce597dc38c Fix try_as_const/as_wire/as_chunk 2025-11-07 15:54:55 +00:00
Robert O'Callahan 0281ed1458 Add try_as_const and use the const iterator a bit more 2025-11-07 15:54:55 +00:00
Robert O'Callahan 0091d14e6d Make SigSpec::has_marked_bits use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 80b3efb3da Make SigSpec::has_const(State) use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan ed8022f53f Make SigSpec::has_const use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 1893c61fe2 Make SigSpec::is_fully_undef use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan e2defe7898 Make SigSpec::is_fully_def use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan 152a487cc8 Make SigSpec::is_fully_ones use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan ddd04e13e0 Make SigSpec::is_fully_zero use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan a7ac396fd9 Make is_fully_const use chunk iterator 2025-11-07 15:54:55 +00:00
Robert O'Callahan b0ee67a355 Make SigSpec::is_wire/is_chunk/is_fully_const use chunk iterator 2025-11-07 15:54:54 +00:00
Robert O'Callahan fc7d61132d Make SigSpec::updhash() use chunk iterator 2025-11-07 15:54:54 +00:00
Robert O'Callahan 3f7af10eda Make SigSpec::chunks() return an object that can be iterated over without packing the SigSpec 2025-11-07 15:54:54 +00:00
Robert O'Callahan 8d4f790951 Make Module stop accessing internals of SigSpec 2025-11-07 13:25:38 +00:00
Mohamed Gaber dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11 2025-10-26 02:39:43 +03:00
Mohamed Gaber d6b9158fa3
pyosys: fix regressions from 0.58 
- consistently use value semantics for objects passed along FFI boundary
  (not ideal but matches previous behavior)
- add new overload of RTLIL::Module: addMemory that does not require a "donor" object
  - the idea is `Module`, `Memory`, `Wire`, `Cell` and `Process` cannot be directly constructed in Python and can only be added to the existing memory hierarchy in `Design` using the `add` methods - `Memory` requiring a donor object was the odd one out here
- fix superclass member wrapping only looking at direct superclass for inheritance instead of recursively checking superclasses
- fix superclass member wrapping not using superclass's denylists
- fix Design's `__str__` function not returning a string
- fix the generator crashing if there's any `std::function` in a header
- misc: add a crude `__repr__` based on `__str__`
 2025-10-26 02:21:40 +03:00
Emil J a80462f27f
Merge pull request #5339 from rocallahan/fast-rtlil-parser 
Rewrite the RTLIL parser for efficiency
 2025-10-08 14:52:37 +02:00
Mohamed Gaber 447a6cb3f0
misc: `WITH_PYTHON` -> `YOSYS_ENABLE_PYTHON` 
For consistency.

Also trying a new thing: only rebuilding objects that use the pybind11 library. The idea is these are the only objects that include the Python/pybind headers and thus the only ones that depend on the Python ABI in any capacity, so other objects can be reused across wheel builds. This has the potential to cut down build times.
 2025-10-03 11:54:44 +03:00
Robert O'Callahan db3d9a1baf When adding named elements to an RTLIL::Module, std::move the name to avoid refcount churn 2025-09-30 21:39:18 +00:00
Robert O'Callahan 6b43fca8df Make the Const string constructor take the string by value and move it into the const 2025-09-30 21:39:18 +00:00
Akash Levy 16215b8786 Merge upstream 2025-09-29 20:58:56 -07:00
Akash Levy 93a24fe275 Put back is_mostly_const 2025-09-29 20:56:58 -07:00
Akash Levy fbc2b71ed4 Revert some stuff 2025-09-29 00:43:49 -07:00
Jannis Harder 86fb2f16f7 bufnorm: Refactor and fix incremental bufNormalize 
This fixes some edge cases the previous version didn't handle properly
by simplifying the logic of determining directly driven wires and
representatives to use as buffer inputs.
 2025-09-29 08:21:28 +02:00
Akash Levy 652a9a63b2 Update to latest and fix all disabled tests 2025-09-28 01:33:08 -07:00
Jannis Harder 9c1d0a2346
Merge pull request #5382 from rocallahan/fix-bounds-check 
Fix off-by-one error in bounds check in `RTLIL::SigChunk::operator[]`
 2025-09-24 08:41:16 +02:00
Robert O'Callahan 0a17205a95 Fix off-by-one error in bounds check 2025-09-23 21:29:57 +00:00
Akash Levy ab006776d0 Bump 2025-09-23 00:40:20 -07:00
Robert O'Callahan effc52fedc Make `ID::` constants be `StaticIdString`s for better optimization. 
Their internal indexes will be known at compile time, like we already support for the `ID()` macro.
 2025-09-23 03:25:16 +00:00
Akash Levy d16ca47549
Merge branch 'YosysHQ:main' into main 2025-09-22 17:47:23 -07:00
Emil J a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 
write_rtlil: don't sort
 2025-09-22 11:14:39 +02:00
Akash Levy 503b0aae20 Use long long int for pyosys 2025-09-21 02:20:13 -07:00
Akash Levy 60d969530b Bump to latest 2025-09-21 01:10:04 -07:00
Jannis Harder d88d6fce87 kernel: Rewrite bufNormalize 
This is a complete rewrite of the RTLIL-kernel-side bufnorm code. This
is done to support inout ports and undirected connections as well as to
allow removal of cells while in bufnorm mode.

This doesn't yet update the (experimental) `bufnorm` pass, so to
manually test the new kernel functionality, it is important to only use
`bufnorm -update` and `bufnorm -reset` which rely entirely on the kernel
functionality. Other modes of the `bufnorm` pass may still fail in the
presence of inout ports or undirected connections.
 2025-09-17 13:56:46 +02:00
Jannis Harder 1251e92e3a Add `$input_port` and `$connect` cell types 2025-09-17 13:56:46 +02:00
Jannis Harder c4f435569f kernel: Add known_driver method to Wire/SigSpec 2025-09-17 13:56:46 +02:00
Jannis Harder 22423b97c1 kernel: Add RTLIL::PortDir for a combined input and output flag 2025-09-17 13:56:46 +02:00
Robert O'Callahan d24488d3a5 Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff() 2025-09-17 03:24:19 +00:00
Emil J. Tywoniak fdbdd193c1 rtlil: add roundtrip test for design -stash and design -save, fix #5321 2025-09-16 15:47:16 +02:00
rhanqtl 11b829ba70 fix(parse): #5234 adjust width of rhs according to lhs 2025-09-16 15:24:23 +02:00
Robert O'Callahan fee2b8992c Stop using `mutable` in `Const`. 
Now that we only call `bitvectorize()` in non-const methods, we can move the casting-away-const to only happen
in `bitvectorize()`, which is deprecated so only some plugins (maybe) are using it.

This means `const` `Const` methods don't change the underlying data, which means
they'll be safe to use from multiple threads if/when we want to do that.
 2025-09-16 03:17:24 +00:00
Robert O'Callahan 29810f1e7c Make Const::is_*() functions work on packed bits without decaying to vector<State> 2025-09-16 03:17:24 +00:00
Robert O'Callahan caaf9a4400 Const::decode_string() doesn't need to call bitvectorize 2025-09-16 03:17:24 +00:00
Robert O'Callahan cb1186aac5 Make Const::as_string work without reducing packed bits to vector<State> 2025-09-16 03:17:24 +00:00
Robert O'Callahan 67a274ed1f Optimize Const::hash_into to hash packed bits efficiently 2025-09-16 03:17:24 +00:00
Robert O'Callahan 9ad83cc67b Fast path for Const::operator== 2025-09-16 03:17:24 +00:00
Robert O'Callahan b597ad777e Make Const::as_bool and Const::as_int work with packed bits without decaying to vector<State> 2025-09-16 03:17:24 +00:00
Robert O'Callahan b06085ab6c Make Const::Const(long long) constructor use packed bits internally if possible 2025-09-16 03:17:24 +00:00
Robert O'Callahan 61caa5e042 Deprecate Const::bitvectorize() 2025-09-16 03:17:23 +00:00
Robert O'Callahan 1e244cd78a Deprecate Const::bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan 6dc9a8bacf Update kernel to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan 514fb8f901 Fix Const::const_iterator tag to be bidirectional_iterator_tag 2025-09-16 03:17:22 +00:00
Akash Levy f5cb0c328f Bump Yosys to latest 2025-09-13 04:35:52 -07:00
Robert O'Callahan e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Akash Levy 1b3375d8df Merge upstream in 2025-09-09 05:50:48 -07:00
Jannis Harder 3ebecb631c Add a compile time check that kernel/constids.inc is sorted 
This is an invariant now required by the ID macro, so it's better to
have an actual check and not rely on a comment at the top of
kernel/constids.inc.
 2025-09-09 09:56:55 +12:00
Robert O'Callahan 23af52c3c8 Use well-known constants in ID macro and make the constant values known at compile time 2025-09-09 09:56:55 +12:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Akash Levy 56caf7cd84 Bump Yosys to latest 2025-08-13 13:37:37 -07:00
Emil J fb024c4d55
Merge pull request #5135 from YosysHQ/emil/ast-ownership 
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
 2025-08-12 10:58:12 +02:00
Krystine Sherwin 22aa9fba3b
test_cell: Support more cell types 
Still unsupported:
- wide muxes (`$_MUX16_` and friends)

Partially supported types have comments in `test_cell.cc`.

Fix `CellTypes::eval() for `$_NMUX_`.
Fix `RTLIL::Cell::fixup_parameters()` for $concat, $bwmux and $bweqx.
 2025-08-12 10:57:58 +12:00
Emil J. Tywoniak 99ab73424d verilog_location: rename location to Location to avoid conflict with Pass::location 2025-08-11 13:34:10 +02:00
Emil J aedc237c7a rtlil: remove comment 
Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak ecec9a760b ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak c8e0ac0c61 ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
Akash Levy cc733fd11b Merge from upstream 2025-07-30 22:50:14 -07:00
Emil J 41295175dc
Merge pull request #5248 from calewis/try_unordereded_map 
Use unordered_map instead of dict for IdString's char* to index storage.
 2025-07-29 18:40:07 +02:00
Drew Lewis 2c8b4d7ad1 Use unordered_map instead of dict for IdString char* to index storage. 
dict is pretty slow when you don't ever need to iterate the container in
order.  And the hashfunction for char* in dict hashes for every single
byte in the string, likely doing significantly more work than std::hash.
 2025-07-29 10:48:44 +02:00
Robert O'Callahan f25f8fe7c4 In the Verilog backend, only sort modules that we're going to emit. 
If you have a large design with a lot of modules and you use the Verilog
backend to emit modules one at a time to separate files, performance is
very low. The problem is that the Verilog backend calls `design->sort()`
every time, which sorts the contents of all modules, and this is slow
even when everything is already sorted.

We can easily fix this by only sorting the contents of modules that
we're actually going to emit.
 2025-07-21 05:32:31 +00:00
Akash Levy 082adf8684
Merge branch 'YosysHQ:main' into main 2025-07-15 00:04:28 -04:00
George Rennie 478b6a2b3f kernel: treat zero width constant as zero 2025-07-08 19:37:59 +01:00
Akash Levy 447a73ea86
Merge branch 'YosysHQ:main' into main 2025-06-09 14:51:56 -07:00
N. Engelhardt 3fe31294d6 disable warning for intentional use of deprecated function (to assert the feature isn't used any more) 2025-06-06 16:41:25 +02:00
Akash Levy c172eea61f
Merge branch 'YosysHQ:main' into main 2025-05-30 05:00:06 +02:00
George Rennie e0c1e88f19 kernel: use try_as_int to implement as_int_compress 2025-05-26 15:34:13 +01:00
George Rennie 33a22b5cd1 kernel: fix convertible_to_int for overflowing unsigned values 2025-05-26 15:28:14 +01:00
Akash Levy d520cb42cc
Merge branch 'YosysHQ:main' into main 2025-05-22 10:30:58 -07:00
Akash Levy c55ee83992 Add Design.run_pass API 2025-05-08 07:20:02 -07:00
George Rennie e2485000c7 kernel: handle unsigned case for as_int_saturating correctly 
* This fixes #5105
 2025-05-08 11:08:25 +02:00
George Rennie 7cbe6ed048 kernel: add safer variants of as_int 2025-05-07 14:39:17 +02:00
Akash Levy 5f5ed1b29e Merge upstream yosys 2025-04-21 17:36:24 -07:00
Akash Levy e241c9d513
Merge branch 'YosysHQ:main' into main 2025-04-10 14:28:10 -07:00
Krystine Sherwin ca57df8927
cutpoint: Add $scopeinfo cell 
Also adds "blackbox" as a valid TYPE.
 2025-04-11 04:12:34 +12:00
Krystine Sherwin 1ef9908a85
rtlil.cc: Fix box checks in selected_modules 2025-04-08 11:59:36 +12:00
Krystine Sherwin cd3b914132
Reinstate #4768 
Revert the reversion so that we can fix the bugs that the PR missed.
 2025-04-08 11:58:05 +12:00
Akash Levy 06c614a010
Merge branch 'YosysHQ:main' into main 2025-04-07 07:28:06 -07:00
Miodrag Milanović d49364d96f
Revert "Refactor full_selection" 2025-04-07 12:11:55 +02:00