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1786 Commits

Author SHA1 Message Date
Jannis Harder 2d81726459 write_xaiger2: Fix output port mapping when opaque boxes are present 2025-09-17 13:10:04 +02:00
Emil J 73e47ac3fe
Merge pull request #5357 from rocallahan/builtin-ff 
Instead of using `builtin_ff_cell_types()` directly, go through a method `Cell::is_builtin_ff()`
 2025-09-17 11:37:16 +02:00
Robert O'Callahan d24488d3a5 Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff() 2025-09-17 03:24:19 +00:00
Robert O'Callahan f80be49fa1 Remove unnecessary .c_str() in EDIF_ macros 2025-09-16 23:14:11 +00:00
Robert O'Callahan a1141f1a4c Remove some unnecessary .c_str() calls to the result of unescape_id() 2025-09-16 23:12:14 +00:00
Robert O'Callahan a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
Robert O'Callahan 5ac6858f26 Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
Emil J. Tywoniak bcc69d5f6e write_rtlil: add -sort to match old behavior 2025-09-16 15:47:16 +02:00
Emil J. Tywoniak 1328a33e82 write_rtlil: dump in insertion order 2025-09-16 15:47:14 +02:00
Emil J. Tywoniak 430adb3b59 write_rtlil: don't sort 2025-09-16 15:39:12 +02:00
Robert O'Callahan 34df6569a6 Update backends to avoid bits() 2025-09-16 03:17:23 +00:00
Akash Levy f5cb0c328f Bump Yosys to latest 2025-09-13 04:35:52 -07:00
Jannis Harder 193b057983
Merge pull request #5341 from rocallahan/more-varargs-conversion 
More varargs conversion
 2025-09-12 18:09:42 +02:00
Robert O'Callahan ff5177ce8e Remove .c_str() from parameters to btorf() and infof() 2025-09-12 05:53:59 +00:00
Robert O'Callahan 6f0c8f56a3 Convert btorf()/infof() to C++ stringf machinery 2025-09-12 05:53:19 +00:00
Robert O'Callahan e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Akash Levy a43de44f9d Merge upstream changes 2025-09-10 23:02:15 -07:00
Robert O'Callahan d34ac0c87d Make `log()` use the `FmtString` infrastructure. 
Now `log()` supports `std::string`.

We have to fix a few places where the format parameter was not a compile time constant.
This is mostly trivial.
 2025-09-09 15:41:03 +02:00
Akash Levy 1b3375d8df Merge upstream in 2025-09-09 05:50:48 -07:00
Akash Levy 8204fd1d0b Update Yosys to latest 2025-09-06 16:49:39 -07:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Jannis Harder 41452e43b2
Merge pull request #4475 from georgerennie/skip_cover 
smtbmc: Support skipping steps in cover mode
 2025-09-01 13:53:04 +02:00
Jannis Harder 501bf4ce40
Merge pull request #4711 from georgerennie/george/btor_buf 
write_btor: support $buf
 2025-09-01 13:38:25 +02:00
Akash Levy e54fa487b8 Merge from upstream 2025-08-21 17:56:55 -07:00
Robert O'Callahan e0e70d1158 Remove some `c_str()` calls where they're no longer needed as parameters to `stringf()`. 2025-08-18 14:20:31 +01:00
Akash Levy 3733ad3879
Merge branch 'YosysHQ:main' into main 2025-08-11 09:26:32 -07:00
Hongce Zhang 76e507f307 update verilog_backend according to Github comments 2025-08-08 16:17:37 +08:00
Akash Levy 77be4d7be7 Bump Yosys to latest 2025-08-07 17:22:25 -07:00
Hongce Zhang b635ab72bf Merge branch 'main' of github.com:zhanghongce/yosys 2025-08-07 11:37:55 +08:00
Hongce Zhang 3cbbb9456d reorder verilog backend port wires 2025-08-07 11:37:23 +08:00
Krystine Sherwin 3959d19291
Reapply "Add groups to command reference" 
This reverts commit 81f87ce6ed.
 2025-08-06 13:52:12 +12:00
Akash Levy cc733fd11b Merge from upstream 2025-07-30 22:50:14 -07:00
Miodrag Milanović 1d229ae254
Merge pull request #5221 from rocallahan/typed-stringf 
Introduce variadic template implementation of `stringf` that supports `std::string` parameters
 2025-07-29 15:12:49 +02:00
Robert O'Callahan 6ee3cd8ffd Replace `stringf()` with a templated function which does compile-time format string checking. 
Checking only happens at compile time if -std=c++20 (or greater) is enabled. Otherwise
the checking happens at run time.

This requires the format string to be a compile-time constant (when compiling with
C++20), so fix a few places where that isn't true.

The format string behavior is a bit more lenient than C printf. For %d/%u
you can pass any integer type and it will be converted and output without
truncating bits, i.e. any length specifier is ignored and the conversion is
always treated as 'll'. Any truncation needs to be done by casting the argument itself.
For %f/%g you can pass anything that converts to double, including integers.

Performance results with clang 19 -O3 on Linux:
```
hyperfine './yosys -dp "read_rtlil /usr/local/google/home/rocallahan/Downloads/jpeg.synth.il; dump"'
```
C++17 before: Time (mean ± σ):     101.3 ms ±   0.8 ms    [User: 85.6 ms, System: 15.6 ms]
C++17 after:  Time (mean ± σ):      98.4 ms ±   1.2 ms    [User: 82.1 ms, System: 16.1 ms]
C++20 before: Time (mean ± σ):     100.9 ms ±   1.1 ms    [User: 87.0 ms, System: 13.8 ms]
C++20 after:  Time (mean ± σ):      97.8 ms ±   1.4 ms    [User: 83.1 ms, System: 14.7 ms]

The generated code is reasonably efficient. E.g. with clang 19, `stringf()` with a format
with no %% escapes and no other parameters (a weirdly common case) often compiles to a fully
inlined `std::string` construction. In general the format string parsing is often (not always)
compiled away.
 2025-07-29 05:29:33 +00:00
N. Engelhardt 81f87ce6ed
Revert "Add groups to command reference" 2025-07-23 14:41:49 +00:00
Robert O'Callahan f25f8fe7c4 In the Verilog backend, only sort modules that we're going to emit. 
If you have a large design with a lot of modules and you use the Verilog
backend to emit modules one at a time to separate files, performance is
very low. The problem is that the Verilog backend calls `design->sort()`
every time, which sorts the contents of all modules, and this is slow
even when everything is already sorted.

We can easily fix this by only sorting the contents of modules that
we're actually going to emit.
 2025-07-21 05:32:31 +00:00
Krystine Sherwin d62a110dc8
register.h: Add internal_flag to Pass 
Update experimental pass warnings to use a shared function.  Reduces repetition, and also allows all of the warning flags to be combined (which at present is just experimental and the new internal).
Update `test_*` passes to call `internal()` in their constructors.
 2025-07-21 10:35:19 +12:00
Akash Levy 37806d5ea7
Merge branch 'YosysHQ:main' into main 2025-07-16 14:59:29 -07:00
George Rennie 381381c997 write_firrtl: clear used names cache each pass 2025-07-15 14:14:07 +01:00
Akash Levy 082adf8684
Merge branch 'YosysHQ:main' into main 2025-07-15 00:04:28 -04:00
Emil J. Tywoniak 2b659626a3 rename: add -unescape 2025-06-24 12:33:33 +02:00
Akash Levy e3a6b920d4
Merge branch 'YosysHQ:main' into main 2025-06-02 18:47:14 +02:00
Emil J c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs 
aiger: fix -map and -vmap
 2025-06-02 15:07:19 +02:00
N. Engelhardt 1c742441db
Merge pull request #5150 from YosysHQ/krys/aiger_ordering 2025-06-02 13:06:36 +00:00
Krystine Sherwin aac562d36a
aiger.cc: Explicit unsorted-pool-as-LIFO 2025-05-31 09:55:00 +12:00
Krystine Sherwin 0072a267cc
write_aiger: Add no-sort option 
Prevents sorting input/output bits so that they remain in the same order they were read in.
 2025-05-29 16:20:16 +12:00
Akash Levy 3fc74be3e2
Merge branch 'YosysHQ:main' into main 2025-05-28 01:54:49 +02:00
gatecat 45a6940f40 cxxrtl: Add debug items for state with private names 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-05-26 16:58:13 +02:00
Akash Levy 3a23e772dd
Merge branch 'YosysHQ:main' into main 2025-05-24 12:11:52 -07:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
Gus Smith d8b27d41c0 Bugfix 2025-05-21 21:31:07 -07:00
Gus Smith 8ec9de00ec Use ir.inputs()/ir.outputs() 2025-05-20 17:45:23 -07:00
Gus Smith af51097af7 Convert to 'assoc list helpers' 2025-05-18 18:01:43 -07:00
Gus Smith a55dc80175 Rename parameter 2025-05-17 16:04:17 -07:00
Gus Smith c1111f125c Add output helper as well 2025-05-17 15:19:09 -07:00
Gus Smith 1fdfba2a1a Add helper for accessing by base name 
The existing access function isn't useful if we don't have access to the original
names of the input/output/state signals. There may be a better way to do this, but
it might require restructuring the SmtrStruct.
 2025-05-17 15:17:29 -07:00
Gus Smith 10b8fdddb4 Rename argument 2025-05-17 14:39:11 -07:00
Gus Smith 7b4c9c5dcd Add optional keyword-based constructor 2025-05-17 14:12:09 -07:00
Gus Smith fd5918c811 get_field_names for structs 2025-05-17 14:10:23 -07:00
Emil J. Tywoniak f73c6a9c9a write_verilog: don't dump single_bit_vector attribute 2025-05-12 13:36:25 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Akash Levy aeed1ddb74 Update from upstream 2025-05-11 15:16:52 -07:00
Emil J. Tywoniak 2522bcd492 aiger: fix -map and -vmap 2025-05-09 14:21:10 +02:00
Emil J. Tywoniak 90a2c92370 driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
Akash Levy 7191be492c
Merge branch 'YosysHQ:main' into main 2025-05-05 15:36:40 -07:00
Emil J. Tywoniak d7affb8821 driver: add --no-version to suppress writing Yosys version in command outputs 2025-05-05 13:12:08 +02:00
sdjasj da1ac9ae47
cxxrtl: fix missing sign extension before shift operation for signed values 2025-05-03 09:38:16 +00:00
Akash Levy 94bc6937d3
Merge branch 'YosysHQ:main' into main 2025-04-27 15:24:30 -07:00
Catherine 3d1f2161dc cxxrtl: strip `$paramod` from module name in scope info. 2025-04-26 14:51:21 +01:00
Akash Levy b8ee17e807
Merge branch 'YosysHQ:main' into main 2025-04-24 14:51:28 -07:00
sdjasj b693947834 fix udivmod crashes when operand value exceeds logical width 2025-04-24 14:33:52 +01:00
Akash Levy 5f5ed1b29e Merge upstream yosys 2025-04-21 17:36:24 -07:00
David Sawatzke 04098933c7 cxxrtl: Add internal cell "bwmux" 
Mirrors the implementation for the smt2 backend

Co-authored-by: Martin Povišer <povik@cutebit.org>
 2025-04-16 13:58:08 +01:00
Akash Levy e241c9d513
Merge branch 'YosysHQ:main' into main 2025-04-10 14:28:10 -07:00
Krystine Sherwin cd3b914132
Reinstate #4768 
Revert the reversion so that we can fix the bugs that the PR missed.
 2025-04-08 11:58:05 +12:00
Akash Levy 06c614a010
Merge branch 'YosysHQ:main' into main 2025-04-07 07:28:06 -07:00
Miodrag Milanović d49364d96f
Revert "Refactor full_selection" 2025-04-07 12:11:55 +02:00
Akash Levy 0dab4308a3 Actual merge here 2025-04-06 18:53:43 -07:00
KrystalDelusion 98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections 
Refactor full_selection
 2025-04-05 14:15:27 +13:00
Akash Levy f218b5ba58 Revert "Represent memory size with size_t" 
This reverts commit bb5f8415af.
 2025-04-04 03:20:07 -07:00
Akash Levy bb5f8415af Represent memory size with size_t 2025-04-04 02:04:34 -07:00
Akash Levy 95f489beec Merge nice gzip refactor 2025-03-20 16:47:12 -07:00
Emil J. Tywoniak 4f3fdc8457 io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
Akash Levy 1c0d4a43b3
Merge branch 'YosysHQ:main' into main 2025-03-14 18:07:55 -07:00
KrystalDelusion 9fa1f0e70c
Merge pull request #4567 from kivikakk/cxxrtl-escape-trailing 
cxxrtl: use octal encoding of non-printables.
 2025-03-14 16:52:07 +13:00
Krystine Sherwin 46a311acb2
firrtl: Drop full_selection check 
Change `top` pointer default to `nullptr` to avoid issues with `Design->top_module()` only operating on the current selection.

Calls to other passes (`bmuxmap` etc) will only operate on the current selection, and may cause problems when those cells are unprocessed, but this is consistent with the other backends that only operate on the full designs and will hopefully be fixed in another PR soon :)
 2025-03-14 14:08:56 +13:00
Krystine Sherwin dac2bb7d4d
Use selection helpers 
Catch more uses of selection constructor without assigning a design.
 2025-03-14 14:08:13 +13:00
Akash Levy e4066b784d Merge remote-tracking branch 'upstream/main' 2025-03-12 19:21:32 -07:00
KrystalDelusion 65748b8387
Merge pull request #4898 from Anhijkt/fix-xaiger-segfault 
write_xaiger: Detect and error on combinatorial loops
 2025-03-13 10:49:48 +13:00
Akash Levy e360511339
Merge branch 'YosysHQ:main' into main 2025-03-10 14:21:49 -07:00
Alain Dargelas 268459e00a write_verilog -srcattronly option 2025-03-10 10:15:24 -07:00
Alain Dargelas 1b1882fe56 write_verilog -srcattronly option 2025-03-10 09:29:48 -07:00
Alain Dargelas e35032f2f6 write_verilog -onlysrcattr option 2025-03-10 09:27:27 -07:00
N. Engelhardt c74df780b7
Merge pull request #4884 from YosysHQ/docs-preview-functional_tutorial 
Docs: More on FunctionalIR
 2025-03-10 15:05:55 +00:00
Anhijkt a8052f653a write_xaiger: Detect and error on combinatorial loops 2025-02-14 01:21:39 +02:00
Krystine Sherwin fa2d45a922
smtr: Refactor write back into _eval and _initial 
Easier for comparisons, and the structure still works.  (I don't remember why I moved away from it in the first place.)
 2025-02-07 13:58:09 +13:00
Akash Levy 66186f11fd
Merge branch 'YosysHQ:main' into main 2025-01-30 14:00:19 -08:00
Robin Ole Heinemann 0ab13924a5 write_verilog: log_abort on unhandled $check flavor 2025-01-30 14:18:02 +00:00
Robin Ole Heinemann 2f11dc87c9 write_verilog: emit $check cell names as labels 2025-01-30 14:18:02 +00:00
Akash Levy f403256a34
Merge branch 'YosysHQ:main' into main 2025-01-23 14:06:16 -08:00