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2435 Commits

Author SHA1 Message Date
Akash Levy ec535c1b48
Merge branch 'YosysHQ:main' into main 2025-11-05 15:40:09 -05:00
Martin Povišer 45bb5c690d
Merge pull request #5460 from povik/timeest-comb 
timeest: Add top ports launching/sampling
 2025-11-05 14:29:34 +01:00
Akash Levy 11731c91f4 Merge from upstream 2025-11-04 22:20:34 -08:00
Akash Levy 4c903fe7f3 Use upstream implementation of logger_cmd_error.sh in tests/various 2025-11-04 22:00:26 -08:00
KrystalDelusion 52c108cd6a
Merge pull request #4596 from YosysHQ/emil/path-sep-refactor 
Refactor getting dirs and filenames from paths to files
 2025-11-05 09:12:54 +13:00
Miodrag Milanović 0751b74e7a
Merge pull request #5441 from donn/pyosys_bugfixes 
pyosys: fix a number of regressions from 0.58
 2025-11-04 07:36:25 +01:00
Krystine Sherwin 1a80c26bae
tests: Fix for macos 
Drop non standard `-t` flag for putting the destination directory first.
 2025-11-04 11:11:01 +13:00
Akash Levy 76c12f8f8c
Merge branch 'YosysHQ:main' into main 2025-11-03 13:38:04 -05:00
Martin Povišer 5fa7feccd3 timeest: Add top ports launching/sampling 2025-11-03 14:21:28 +01:00
Miodrag Milanović d0a41d4f58
Merge pull request #5442 from rocallahan/verific-bus-ports 
Set `port_id` for Verific `PortBus` wires
 2025-11-03 10:04:07 +01:00
Emil J. Tywoniak b2fe335b2d dfflibmap: fix next_state inversion propagation for DFF flops by inverting reset value polarity 2025-10-28 13:56:28 +01:00
Akash Levy 3d06b52ae1 Fix broken Yosys test 2025-10-26 11:40:13 -07:00
Mohamed Gaber dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11 2025-10-26 02:39:43 +03:00
Mohamed Gaber d6b9158fa3
pyosys: fix regressions from 0.58 
- consistently use value semantics for objects passed along FFI boundary
  (not ideal but matches previous behavior)
- add new overload of RTLIL::Module: addMemory that does not require a "donor" object
  - the idea is `Module`, `Memory`, `Wire`, `Cell` and `Process` cannot be directly constructed in Python and can only be added to the existing memory hierarchy in `Design` using the `add` methods - `Memory` requiring a donor object was the odd one out here
- fix superclass member wrapping only looking at direct superclass for inheritance instead of recursively checking superclasses
- fix superclass member wrapping not using superclass's denylists
- fix Design's `__str__` function not returning a string
- fix the generator crashing if there's any `std::function` in a header
- misc: add a crude `__repr__` based on `__str__`
 2025-10-26 02:21:40 +03:00
Robert O'Callahan 25aafab86b Set `port_id` for Verific PortBus wires 2025-10-23 20:51:53 +00:00
Jannis Harder 6a0ee6e4fb Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
Miodrag Milanovic f11a61b32b sim: Make cycle width small as possible and configurable 2025-10-16 11:37:44 +02:00
Miodrag Milanović 759996b968
Merge pull request #5427 from donn/plugin_search_paths 
plugins: add search paths
 2025-10-15 20:02:05 +02:00
Emil J 9d21585a4c
Merge pull request #5426 from rocallahan/parse-sigspec 
Don't stop parsing sigspec after a {} group.
 2025-10-15 17:31:11 +02:00
Mohamed Gaber e86797f029
plugins: add search path 
This uses the environment variable `YOSYS_PLUGIN_PATH` to provide multiple colon-delimited search paths for native plugins in a similar manner to `PATH` for executables and `PYTHONPATH` for Python modules.

This addresses https://github.com/YosysHQ/yosys/issues/2545, allowing Yosys to be better packaged in non-FHS environments such as Nix.
 2025-10-15 14:13:25 +03:00
Robert O'Callahan e099a7d34a Don't stop parsing sigspec after a {} group. 
Resolves #5424
 2025-10-14 21:18:58 +00:00
Miodrag Milanović 2e3bfca294
Merge pull request #5419 from YosysHQ/micko/verific_fix_nocolumns 
verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
 2025-10-14 17:05:31 +02:00
Miodrag Milanovic 7d2857b30f Fix regex checks 2025-10-14 16:04:56 +02:00
N. Engelhardt 4513783a02 add tests 2025-10-14 15:48:16 +02:00
Krystine Sherwin 1eb5181700 Add tests/verilog/local_include.* 
`read_verilog` supports checking both the current directory and the source directory for relative includes.  Make sure we aren't regressing that.
 2025-10-14 15:47:08 +02:00
Emil J. Tywoniak e9aedf505c chtype: replace publish pass with chtype -publish_icells 2025-10-14 15:01:48 +02:00
Emil J. Tywoniak c46df9ffdc box_derive: rename -apply to -apply_derived_type 2025-10-13 17:24:32 +02:00
Emil J. Tywoniak d7cea2c35c box_derive: add -apply 2025-10-13 17:24:32 +02:00
Emil J 9a12d92551
Merge pull request #5386 from YosysHQ/emil/liberty-glob-all 
Expand wildcards in Liberty file consumers
 2025-10-09 20:21:48 +02:00
Miodrag Milanović ba1a347d59
Merge pull request #5370 from donn/pyosys_pybind11 
pyosys: rewrite using pybind11
 2025-10-08 13:07:59 +02:00
Miodrag Milanović 4cdaac003f
Merge pull request #3991 from adrianparvino/alumacc-sign 
alumacc: merge independent of sign
 2025-10-08 13:02:10 +02:00
Mohamed Gaber 80fcce64da
pyosys: fix ref-only classes, implicit conversions 
+ cleanup
 2025-10-03 11:54:44 +03:00
Mohamed Gaber c8404bf86b
pyosys/hashlib: equivalence operators 2025-10-03 11:54:44 +03:00
Mohamed Gaber dc88906c91
tests/pyosys: print log on failed test, fix make clean 2025-10-03 11:54:44 +03:00
Mohamed Gaber 54799bb8be
pyosys: globals, set operators for opaque types 
There is so much templating going on that compiling wrappers.cc now takes 1m1.668s on an Apple M4…
 2025-10-03 11:54:44 +03:00
Mohamed Gaber 384f7431fd
pyosys: rewrite wrapper generator 
[skip ci]
 2025-10-03 11:54:44 +03:00
Mohamed Gaber 88be728353
pyosys: rewrite using pybind11 
- Rewrite all Python features to use the pybind11 library instead of boost::python.
  Unlike boost::python, pybind11 is a header-only library that is just included by Pyosys code, saving a lot of compile time on wheels.
- Factor out as much "translation" code from the generator into proper C++ files
- Fix running the embedded interpreter not supporting "from pyosys import libyosys as ys" like wheels
- Move Python-related elements to `pyosys` directory at the root of the repo
- Slight shift in bridging semantics:
  - Containers are declared as "opaque types" and are passed by reference to Python - many methods have been implemented to make them feel right at home without the overhead/ambiguity of copying to Python and then copying back after mutation
  - Monitor/Pass use "trampoline" pattern to support virual methods overridable in Python: virtual methods no longer require `py_` prefix
- Create really short test set for pyosys that just exercises basic functionality
 2025-10-03 11:54:44 +03:00
Akash Levy 6021168b03 Add back VHDL support 2025-10-02 00:39:33 -07:00
Akash Levy a353716202 Update fanoutbuf 2025-10-01 20:59:36 -07:00
Akash Levy c8d8c4f408 Add fanoutbuf pass 2025-10-01 19:23:45 -07:00
Akash Levy 17e3ed3258 Remove annotate_unqcoef (for now) 2025-10-01 19:23:13 -07:00
Akash Levy 40f562475e Smallfix 2025-09-30 14:18:23 -07:00
Akash Levy 16215b8786 Merge upstream 2025-09-29 20:58:56 -07:00
Jannis Harder 47639f8a98
Merge pull request #5388 from jix/bufnorm-followup 
Refactor and fixes to incremental bufNormalize + related changes
 2025-09-29 15:15:29 +02:00
Jannis Harder 6a7372626a
Merge pull request #5389 from jix/sva_continue 
verific: New `-sva-continue-on-error` import option
 2025-09-29 15:07:54 +02:00
Akash Levy dfc8607a77 Fixups 2025-09-29 03:49:44 -07:00
Martin Povišer ffe2f7a16d opt_hier: Fix two optimizations conflicting 
Fix a conflict between the following two:

 * propagation of tied-together inputs in
 * propagation of unused inputs out
 2025-09-29 12:27:27 +02:00
Akash Levy fbc2b71ed4 Revert some stuff 2025-09-29 00:43:49 -07:00
Jannis Harder 86fb2f16f7 bufnorm: Refactor and fix incremental bufNormalize 
This fixes some edge cases the previous version didn't handle properly
by simplifying the logic of determining directly driven wires and
representatives to use as buffer inputs.
 2025-09-29 08:21:28 +02:00
Akash Levy a0d1c8b30f More minor cleanup 2025-09-28 07:19:53 -07:00