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Smallfix
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@ -905,28 +905,6 @@ select t:$sub -assert-count 0
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design -reset
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log -pop
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log -header "Test with parameters/generics"
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log -push
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design -reset
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read_verilog <<EOF
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module top #(parameter WIDTH = 8) (
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input wire [WIDTH-1:0] a,
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output wire [WIDTH+2:0] y
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);
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wire [WIDTH+2:0] temp;
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assign temp = a + 5;
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assign y = temp + 3;
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endmodule
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EOF
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check -assert
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wreduce
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equiv_opt -assert peepopt
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design -load postopt
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select t:$add -assert-count 1
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select t:$sub -assert-count 0
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design -reset
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log -pop
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log -header "Final test case"
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log -push
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design -reset
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