mirror of https://github.com/YosysHQ/yosys.git
Add fanoutbuf pass
This commit is contained in:
Akash Levy
parent
17e3ed3258
commit
c8d8c4f408
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@ -5,6 +5,7 @@ OBJS += passes/silimate/annotate_logic_depth.o
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OBJS += passes/silimate/breakreduce.o
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OBJS += passes/silimate/breaksop.o
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OBJS += passes/silimate/bus_rebuild.o
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OBJS += passes/silimate/fanoutbuf.o
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OBJS += passes/silimate/lut2bmux.o
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OBJS += passes/silimate/obs_clean.o
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OBJS += passes/silimate/opt_balance_tree.o
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@ -0,0 +1,197 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* 2025 Akash Levy <akash@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct FanoutbufPass : public Pass {
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FanoutbufPass() : Pass("fanoutbuf", "insert $buf cells to limit fanout") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fanoutbuf [options] [selection]\n");
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log("\n");
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log("This command inserts $buf cells to limit fanout while minimizing the number of");
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log("buffers inserted.\n");
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log("\n");
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log(" -limit n\n");
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log(" max fanout to allow (default: 4).\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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int limit = 4;
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log_header(design, "Executing FANOUTBUF pass (inserting buffers to limit fanout).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-limit" && argidx+1 < args.size()) {
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limit = std::stoi(args[++argidx]);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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// Add $pos cells on input ports and output ports
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vector<Wire *> ports;
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vector<Cell *> iobufs;
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for (auto port : module->ports) {
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auto wire = module->wire(port);
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if (wire->port_input) {
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auto new_in = module->addWire(module->uniquify(wire->name.str() + "_new"), wire);
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auto iobuf = module->addPos(module->uniquify(wire->name.str() + "_in"), new_in, wire);
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iobufs.push_back(iobuf);
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module->swap_names(wire, new_in);
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wire->port_input = false;
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}
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if (wire->port_output) {
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auto new_out = module->addWire(module->uniquify(wire->name.str() + "_new"), wire);
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auto iobuf = module->addPos(module->uniquify(wire->name.str() + "_out"), wire, new_out);
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iobufs.push_back(iobuf);
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module->swap_names(wire, new_out);
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wire->port_output = false;
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}
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}
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module->fixup_ports();
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// Data structures for splitting fanout
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SigMap sigmap(module);
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dict<SigBit, pool<tuple<IdString,IdString,int>>> bit_users_db;
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int bufcount = 0;
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// Build bit_users_db
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log_debug("Building bit_users_db...\n");
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for (auto cell : module->cells()) {
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for (auto conn : cell->connections()) {
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if (!cell->input(conn.first)) continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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bit_users_db[bit].insert(tuple<IdString,IdString,int>(cell->name, conn.first, i));
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}
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}
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}
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// Queue up all cells
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std::set<Cell*, IdString::compare_ptr_by_name<Cell>> work_queue_cells;
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for (auto cell : module->selected_cells())
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work_queue_cells.insert(cell);
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// Split fanout with BFS
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while (!work_queue_cells.empty()) {
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auto cell = *work_queue_cells.begin();
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work_queue_cells.erase(work_queue_cells.begin());
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for (auto conn : cell->connections()) {
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if (!cell->output(conn.first)) continue;
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for (auto bit : sigmap(conn.second)) {
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// Collect targets
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auto targets = bit_users_db[bit];
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log("Cell, targets: %s, %d\n", log_id(cell), GetSize(targets));
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bit_users_db[bit].clear();
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// If there are less than limit targets, no need to split
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if (GetSize(targets) <= limit)
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continue;
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// Set up buffers
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int nbufs = std::min(limit, GetSize(targets) / limit);
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vector<Wire *> bufouts(nbufs, nullptr);
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for (int i = 0; i < nbufs; i++) {
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// New buffer name should be unique and short
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IdString buf_name;
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if (cell->type == ID::$_BUF_)
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buf_name = NEW_ID2;
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else
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buf_name = NEW_ID2_SUFFIX("fbuf");
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// Create buffer, connect input to bit and output to new wire
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Wire *bufout = module->addWire(buf_name.str() + "_out");
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Cell *buf = module->addBuf(buf_name, bit, bufout, false, cell->get_src_attribute());
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sigmap.add(bufout);
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work_queue_cells.insert(buf);
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bufouts[i] = bufout;
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bufcount++;
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}
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// Target limit is initialized to limit
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// Gets multiplied by limit each time the current set of buffers is saturated
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int target_limit = limit;
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int target_i = 0;
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int cur_buf_i = 0;
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vector<int> current_fanout(nbufs, 0);
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for (auto target : targets) {
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// If there are less buffers than the limit, keep a few targets on the original cell
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bool skip_target = false;
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if (target_i < limit - nbufs) {
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target_i++;
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skip_target = true;
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}
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if (skip_target)
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continue;
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// Search for a buffer with fanout less than target_limit
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while (current_fanout[cur_buf_i] >= target_limit) {
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cur_buf_i++;
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// If we've reached the end of the buffers, reset to the start
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// and increase target limit
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if (cur_buf_i >= nbufs) {
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cur_buf_i = 0;
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target_limit *= limit;
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}
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}
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// Replace bit in target cell with buffered output
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auto target_cell = module->cell(std::get<0>(target));
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auto target_port = std::get<1>(target);
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auto target_bit_idx = std::get<2>(target);
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auto new_cell_in = target_cell->getPort(target_port);
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new_cell_in[target_bit_idx] = bufouts[cur_buf_i];
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target_cell->setPort(target_port, new_cell_in);
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bit_users_db[bufouts[cur_buf_i]].insert(
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tuple<IdString,IdString,int>(target_cell->name, target_port, target_bit_idx)
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);
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sigmap.add(bufouts[cur_buf_i], new_cell_in[target_bit_idx]);
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// Increment fanout for current buffer
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current_fanout[cur_buf_i]++;
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}
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}
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}
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}
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// Remove $pos cells
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for (auto cell : iobufs) {
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if (cell->type == ID::$pos) {
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module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
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module->remove(cell);
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}
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}
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// Log number of buffers inserted
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log("Inserted %d buffers in module '%s'.\n", bufcount, log_id(module));
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}
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}
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} FanoutbufPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,402 @@
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# Test 1
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log -header "Simple input to output buffer > limit 4"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 2
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log -header "Simple input to output buffer = limit 4, should do nothing"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-none t:$buf
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design -reset
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log -pop
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# Test 3
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log -header "Simple input to output buffer = limit 4*4 + 1 = 17, should do two layers"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5,
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output wire w6,
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output wire w7,
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output wire w8,
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output wire w9,
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output wire w10,
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output wire w11,
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output wire w12,
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output wire w13,
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output wire w14,
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output wire w15,
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output wire w16,
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output wire w17
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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assign w6 = a;
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assign w7 = a;
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assign w8 = a;
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assign w9 = a;
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assign w10 = a;
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assign w11 = a;
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assign w12 = a;
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assign w13 = a;
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assign w14 = a;
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assign w15 = a;
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assign w16 = a;
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assign w17 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 5 t:$buf
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design -reset
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log -pop
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# Test 4
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log -header "Multi-bit signal fanout buffering"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire [3:0] w1,
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output wire [3:0] w2,
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output wire [3:0] w3,
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output wire [3:0] w4,
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output wire [3:0] w5
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should have 4 buffers (one per bit)
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 4 t:$buf
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design -reset
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log -pop
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# Test 5
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log -header "Custom fanout limit (limit 3)"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf with limit 3 - should insert 1 buffer
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equiv_opt -assert fanoutbuf -limit 3
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 6
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log -header "Mixed fanout counts on different signals"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5,
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output wire x1,
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output wire x2
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);
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assign w1 = a; // a has fanout 5 (> limit 4)
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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assign x1 = b; // b has fanout 2 (< limit 4)
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assign x2 = b;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should insert 1 buffer for signal a only
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 7
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log -header "Logic gates with high fanout"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5,
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output wire w6
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);
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wire and_out;
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assign and_out = a & b;
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assign w1 = and_out;
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assign w2 = and_out;
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assign w3 = and_out;
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assign w4 = and_out;
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assign w5 = and_out;
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assign w6 = and_out;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should insert buffers for and_out
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 8
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log -header "Edge case: exactly limit+1 fanout"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should insert exactly 1 buffer
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 9
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log -header "Complex expressions with intermediate signals"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5,
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output wire x1,
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output wire x2,
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output wire x3,
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output wire x4,
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output wire x5
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);
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wire intermediate1, intermediate2;
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assign intermediate1 = a & b;
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assign intermediate2 = intermediate1 | c;
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assign w1 = intermediate1;
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assign w2 = intermediate1;
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assign w3 = intermediate1;
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assign w4 = intermediate1;
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assign w5 = intermediate1;
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||||
|
||||
assign x1 = intermediate2;
|
||||
assign x2 = intermediate2;
|
||||
assign x3 = intermediate2;
|
||||
assign x4 = intermediate2;
|
||||
assign x5 = intermediate2;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after fanoutbuf - should insert buffers for both intermediates
|
||||
equiv_opt -assert fanoutbuf
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$buf
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
# Test 10
|
||||
log -header "Hierarchical design with fanout buffering"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module sub (
|
||||
input wire in,
|
||||
output wire out1,
|
||||
output wire out2,
|
||||
output wire out3,
|
||||
output wire out4,
|
||||
output wire out5
|
||||
);
|
||||
assign out1 = in;
|
||||
assign out2 = in;
|
||||
assign out3 = in;
|
||||
assign out4 = in;
|
||||
assign out5 = in;
|
||||
endmodule
|
||||
|
||||
module top (
|
||||
input wire a,
|
||||
output wire w1,
|
||||
output wire w2,
|
||||
output wire w3,
|
||||
output wire w4,
|
||||
output wire w5
|
||||
);
|
||||
sub u1 (.in(a), .out1(w1), .out2(w2), .out3(w3), .out4(w4), .out5(w5));
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after fanoutbuf - should insert buffers in sub module
|
||||
equiv_opt -assert fanoutbuf
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$buf
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
# Test 11
|
||||
log -header "Very high fanout requiring multiple buffer layers"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire a,
|
||||
output wire [31:0] w
|
||||
);
|
||||
assign w = {32{a}}; // 32-bit fanout from single input
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Check equivalence after fanoutbuf - should insert multiple layers of buffers
|
||||
equiv_opt -assert fanoutbuf
|
||||
design -load postopt
|
||||
select -assert-min 8 t:$buf
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue