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891 Commits

Author SHA1 Message Date
Akash Levy 1dd846022b Fix opt_dff cell naming 2026-01-28 23:36:49 -08:00
Akash Levy 9f911e3d63 Reorder ff.remove in opt_dff 2026-01-28 20:58:01 -08:00
Akash Levy 16087ae931 Merge from upstream 2026-01-28 18:17:50 -08:00
Akash Levy 26f5ff3d74 Merge from upstream 2026-01-26 22:16:11 -08:00
Robert O'Callahan 32e96605d4 Don't update `used_signals` for retained wires in `rmunused_module_signals`. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Akash Levy 5a6dffeecd Silimate mods to upstream opt_balance_tree pass 2026-01-21 23:34:34 -08:00
Akash Levy b11037e6c6 Merge remote-tracking branch 'upstream/main' 2026-01-21 15:13:57 -08:00
Emil J. Tywoniak c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width 
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
 2026-01-14 14:58:53 -08:00
Natalia 60ac3670cb Fix truncation issue in opt_balance_tree pass 
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.

For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)

Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
 2026-01-14 13:14:56 -08:00
Natalia Kokoromyti 6aef8ea8ab Add missing <deque> include for MSVC compatibility 2026-01-13 15:31:46 -08:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Akash Levy a121255f47
Merge branch 'YosysHQ:main' into main 2026-01-13 11:28:34 -08:00
Emil J. Tywoniak 8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Akash Levy 58192ad8a6
Merge branch 'YosysHQ:main' into main 2026-01-12 22:52:03 -08:00
Robert O'Callahan 8da919587d Parallelize `opt_merge`. 
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
 2026-01-08 04:21:39 +00:00
Akash Levy e332ba807d
Merge branch 'YosysHQ:main' into main 2026-01-07 12:40:39 -08:00
Emil J 5c630a366d
Merge pull request #5555 from rocallahan/defer-redirects 
Defer redirecting cell outputs when merging cells in `opt_merge` untill after we've done a full pass over the cells.
 2026-01-06 18:48:16 +01:00
Robert O'Callahan 042ec1cf60 Defer redirecting cell outputs when merging cells in `opt_merge` until after we've done a full pass over the cells. 
This avoids changing `assign_map` and `initvals`, which are inputs to the hash function for `known_cells`,
while `known_cells` exists. Changing the hash function for a hashtable while it exists leads to
confusing behavior. That also means the exact behavior of `opt_merge` cannot be reproduced by a
parallel implementation.
 2026-01-06 16:21:48 +00:00
Akash Levy 1941e8f042 Bump yosys and abc to latest 2025-12-25 03:46:16 -05:00
N. Engelhardt 45d654e2d7 avoid merging formal properties 2025-12-17 20:25:24 +01:00
Akash Levy b3e669c2f3 Ok actually done now 2025-12-05 20:25:56 -08:00
Akash Levy 2aeada6980 Bump Yosys to latest 2025-12-05 20:05:16 -08:00
Robert O'Callahan 638e904f91 Remove cover() coverage tracking 2025-12-04 16:27:13 +01:00
Akash Levy 71586d39b0 Merge from upstream 2025-11-12 08:14:33 -08:00
Robert O'Callahan 325b27f43a Avoid calling IdString::c_str() in opt_clean 2025-11-12 11:52:04 +01:00
Robert O'Callahan 54bde15329 Implement IdString garbage collection instead of refcounting. 2025-11-12 11:52:04 +01:00
Akash Levy dee059bee8 Fix minor Yosys issues 2025-09-30 12:05:36 -07:00
Akash Levy c26f38faeb
Merge branch 'YosysHQ:main' into main 2025-09-30 11:14:33 -07:00
Emil J 7719beb4ae
Merge pull request #5349 from rocallahan/cleanup-hashops 
Reduce hashops verbiage in `OptMergePass`
 2025-09-30 19:34:44 +02:00
Akash Levy 16215b8786 Merge upstream 2025-09-29 20:58:56 -07:00
Akash Levy 313c7e4b95 Fix wreduce using queueing algorithm 2025-09-29 20:28:55 -07:00
Akash Levy d36bc8231f Revert wreduce to initial state 2025-09-29 12:44:30 -07:00
Jannis Harder 47639f8a98
Merge pull request #5388 from jix/bufnorm-followup 
Refactor and fixes to incremental bufNormalize + related changes
 2025-09-29 15:15:29 +02:00
Emil J 87c1a868d3
Merge pull request #5384 from rocallahan/simplify-opt-merge-logic 
Move `OptMerge` cell filtering logic to happen while building the cell vector
 2025-09-29 15:03:01 +02:00
Akash Levy ded986c510 Probably not fast but it works 2025-09-29 04:39:07 -07:00
Akash Levy b2f2d6d6e3 Actually fix wreduce 2025-09-29 04:16:18 -07:00
Akash Levy dfc8607a77 Fixups 2025-09-29 03:49:44 -07:00
Martin Povišer a9318db2fa opt_hier: Adjust messages 2025-09-29 12:27:27 +02:00
Martin Povišer ffe2f7a16d opt_hier: Fix two optimizations conflicting 
Fix a conflict between the following two:

 * propagation of tied-together inputs in
 * propagation of unused inputs out
 2025-09-29 12:27:27 +02:00
Akash Levy 0b0c7bd19d Fix wreduce speed issue 2025-09-29 00:18:48 -07:00
Akash Levy b5f3d7ee9c Revert three passes 2025-09-29 00:18:34 -07:00
Jannis Harder cbc1055517 opt_clean: Fix debug output when cleaning up bufnorm cells 2025-09-29 08:21:28 +02:00
Akash Levy 652a9a63b2 Update to latest and fix all disabled tests 2025-09-28 01:33:08 -07:00
Akash Levy ae2ed5e82a Fix wreduce speed more 2025-09-27 17:59:25 -07:00
Akash Levy f7dbfcb278 Fix wreduce speed issue 2025-09-26 07:55:37 -07:00
Robert O'Callahan 4d209c187d Switch OptMergeWorker cell type switching to use IdString::in() 2025-09-25 03:06:58 +00:00
Robert O'Callahan 1c73011e7e Swap SigSpecs using std::swap with moves 2025-09-25 03:04:17 +00:00
Robert O'Callahan e9aacd8a05 Move `OptMerge` cell filtering logic to happen while building the cell vector. 
This code is quite confusing because there are two "is the cell known" filters
applied, one while building the cell vector and one after building the cell
vector, and they're subtly different. I'm preserving the actual behaviour here
but it looks like there is, or was, a bug here.
 2025-09-23 23:26:47 +00:00
Robert O'Callahan 1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00