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Bump Yosys to latest

This commit is contained in:
Akash Levy 2025-12-05 20:05:16 -08:00
parent 5dfadb968f 0e31e389f2
commit 2aeada6980
11 changed files with 100 additions and 561 deletions
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10
Makefile
View File

@ -24,7 +24,6 @@ ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0
ENABLE_VERIFIC_EDIF := 0
ENABLE_VERIFIC_LIBERTY := 0
ENABLE_VERIFIC_UPF := 0
ENABLE_COVER := 1
ENABLE_LIBYOSYS := 0
ENABLE_LIBYOSYS_STATIC := 0
ENABLE_ZLIB := 1
@ -178,7 +177,7 @@ ifeq ($(OS), Haiku)
CXXFLAGS += -D_DEFAULT_SOURCE
endif
YOSYS_VER := 0.60+0
YOSYS_VER := 0.60+8
YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
@ -265,9 +264,6 @@ ifneq ($(SANITIZER),)
$(info [Clang Sanitizer] $(SANITIZER))
CXXFLAGS += -g -O1 -fno-omit-frame-pointer -fno-optimize-sibling-calls -fsanitize=$(SANITIZER)
LINKFLAGS += -g -fsanitize=$(SANITIZER)
ifneq ($(findstring address,$(SANITIZER)),)
ENABLE_COVER := 0
endif
ifneq ($(findstring memory,$(SANITIZER)),)
CXXFLAGS += -fPIE -fsanitize-memory-track-origins
LINKFLAGS += -fPIE -fsanitize-memory-track-origins
@ -579,10 +575,6 @@ LIBS_VERIFIC += -Wl,--whole-archive $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VE
endif
endif
ifeq ($(ENABLE_COVER),1)
CXXFLAGS += -DYOSYS_ENABLE_COVER
endif
ifeq ($(ENABLE_CCACHE),1)
CXX := ccache $(CXX)
else

14
backends/aiger2/aiger.cc
View File

@ -24,6 +24,7 @@
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -845,11 +846,14 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
return false;
int max = 1;
for (auto wire : mod->wires())
if (wire->port_input && !wire->port_output)
for (int i = 0; i < wire->width; i++) {
int ilevel = visit(cursor, driver->getPort(wire->name)[i]);
max = std::max(max, ilevel + 1);
for (auto wire : mod->wires()) {
if (wire->port_input && !wire->port_output) {
SigSpec port = driver->getPort(wire->name);
for (int i = 0; i < std::min(wire->width, port.size()); i++) {
int ilevel = visit(cursor, port[i]);
max = std::max(max, ilevel + 1);
}
}
}
lits[idx] = max;

27
kernel/driver.cc
View File

@ -764,33 +764,6 @@ int main(int argc, char **argv)
}
}
#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))
if (getenv("YOSYS_COVER_DIR") || getenv("YOSYS_COVER_FILE"))
{
string filename;
FILE *f;
if (getenv("YOSYS_COVER_DIR")) {
filename = stringf("%s/yosys_cover_%d_XXXXXX.txt", getenv("YOSYS_COVER_DIR"), getpid());
filename = make_temp_file(filename);
} else {
filename = getenv("YOSYS_COVER_FILE");
}
f = fopen(filename.c_str(), "a+");
if (f == NULL)
log_error("Can't create coverage file `%s'.\n", filename);
log("<writing coverage file \"%s\">\n", filename);
for (auto &it : get_coverage_data())
fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str());
fclose(f);
}
#endif
log_check_expected();
yosys_atexit();

51
kernel/log.cc
View File

@ -681,55 +681,4 @@ void log_check_expected()
check_err("prefixed error", pattern, item);
}
// ---------------------------------------------------
// This is the magic behind the code coverage counters
// ---------------------------------------------------
#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))
dict<std::string, std::pair<std::string, int>> extra_coverage_data;
void cover_extra(std::string parent, std::string id, bool increment) {
if (extra_coverage_data.count(id) == 0) {
for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++)
if (p->id == parent)
extra_coverage_data[id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
log_assert(extra_coverage_data.count(id));
}
if (increment)
extra_coverage_data[id].second++;
}
dict<std::string, std::pair<std::string, int>> get_coverage_data()
{
dict<std::string, std::pair<std::string, int>> coverage_data;
for (auto &it : pass_register) {
std::string key = stringf("passes.%s", it.first);
coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__);
coverage_data[key].second += it.second->call_counter;
}
for (auto &it : extra_coverage_data) {
if (coverage_data.count(it.first))
log_warning("found duplicate coverage id \"%s\".\n", it.first);
coverage_data[it.first].first = it.second.first;
coverage_data[it.first].second += it.second.second;
}
for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) {
if (coverage_data.count(p->id))
log_warning("found duplicate coverage id \"%s\".\n", p->id);
coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
coverage_data[p->id].second += p->counter.load(std::memory_order_relaxed);
}
for (auto &it : coverage_data)
if (!it.second.first.compare(0, strlen(YOSYS_SRC "/"), YOSYS_SRC "/"))
it.second.first = it.second.first.substr(strlen(YOSYS_SRC "/"));
return coverage_data;
}
#endif
YOSYS_NAMESPACE_END

48
kernel/log.h
View File

@ -295,54 +295,6 @@ void log_abort_internal(const char *file, int line);
#define log_ping() YOSYS_NAMESPACE_PREFIX log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__)
// ---------------------------------------------------
// This is the magic behind the code coverage counters
// ---------------------------------------------------
#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))
#define cover(_id) do { \
static CoverData __d __attribute__((section("yosys_cover_list"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \
__d.counter.fetch_add(1, std::memory_order_relaxed); \
} while (0)
struct CoverData {
const char *file, *func, *id;
int line;
std::atomic<int> counter;
};
// this two symbols are created by the linker __start_yosys_cover_listfor the "yosys_cover_list" ELF section
extern "C" struct CoverData __start_yosys_cover_list[];
extern "C" struct CoverData __stop_yosys_cover_list[];
extern dict<std::string, std::pair<std::string, int>> extra_coverage_data;
void cover_extra(std::string parent, std::string id, bool increment = true);
dict<std::string, std::pair<std::string, int>> get_coverage_data();
#define cover_list(_id, ...) do { cover(_id); \
std::string r = cover_list_worker(_id, __VA_ARGS__); \
log_assert(r.empty()); \
} while (0)
static inline std::string cover_list_worker(std::string, std::string last) {
return last;
}
template<typename... T>
std::string cover_list_worker(std::string prefix, std::string first, T... rest) {
std::string selected = cover_list_worker(prefix, rest...);
cover_extra(prefix, prefix + "." + first, first == selected);
return first == selected ? "" : selected;
}
#else
# define cover(...) do { } while (0)
# define cover_list(...) do { } while (0)
#endif
// ------------------------------------------------------------
// everything below this line are utilities for troubleshooting
// ------------------------------------------------------------

190
kernel/rtlil.cc
View File

@ -885,8 +885,6 @@ RTLIL::State RTLIL::Const::const_iterator::operator*() const {
bool RTLIL::Const::is_fully_zero() const
{
cover("kernel.rtlil.const.is_fully_zero");
if (auto str = get_if_str()) {
for (char ch : *str)
if (ch != 0)
@ -905,8 +903,6 @@ bool RTLIL::Const::is_fully_zero() const
bool RTLIL::Const::is_fully_ones() const
{
cover("kernel.rtlil.const.is_fully_ones");
if (auto str = get_if_str()) {
for (char ch : *str)
if (ch != (char)0xff)
@ -924,8 +920,6 @@ bool RTLIL::Const::is_fully_ones() const
bool RTLIL::Const::is_fully_def() const
{
cover("kernel.rtlil.const.is_fully_def");
if (is_str())
return true;
@ -939,8 +933,6 @@ bool RTLIL::Const::is_fully_def() const
bool RTLIL::Const::is_fully_undef() const
{
cover("kernel.rtlil.const.is_fully_undef");
if (auto str = get_if_str())
return str->empty();
@ -954,8 +946,6 @@ bool RTLIL::Const::is_fully_undef() const
bool RTLIL::Const::is_fully_undef_x_only() const
{
cover("kernel.rtlil.const.is_fully_undef_x_only");
if (auto str = get_if_str())
return str->empty();
@ -969,8 +959,6 @@ bool RTLIL::Const::is_fully_undef_x_only() const
bool RTLIL::Const::is_onehot(int *pos) const
{
cover("kernel.rtlil.const.is_onehot");
bool found = false;
int size = GetSize(*this);
for (int i = 0; i < size; i++) {
@ -4705,8 +4693,6 @@ bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
{
cover("kernel.rtlil.sigspec.init.list");
init_empty_bits();
log_assert(parts.size() > 0);
auto ie = parts.begin();
@ -4717,8 +4703,6 @@ RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
{
cover("kernel.rtlil.sigspec.init.const");
if (GetSize(value) != 0) {
rep_ = CHUNK;
new (&chunk_) RTLIL::SigChunk(value);
@ -4730,8 +4714,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
RTLIL::SigSpec::SigSpec(RTLIL::Const &&value)
{
cover("kernel.rtlil.sigspec.init.const.move");
if (GetSize(value) != 0) {
rep_ = CHUNK;
new (&chunk_) RTLIL::SigChunk(value);
@ -4743,8 +4725,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Const &&value)
RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
{
cover("kernel.rtlil.sigspec.init.chunk");
if (chunk.width != 0) {
rep_ = CHUNK;
new (&chunk_) RTLIL::SigChunk(chunk);
@ -4756,8 +4736,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
RTLIL::SigSpec::SigSpec(RTLIL::SigChunk &&chunk)
{
cover("kernel.rtlil.sigspec.init.chunk.move");
if (chunk.width != 0) {
rep_ = CHUNK;
new (&chunk_) RTLIL::SigChunk(chunk);
@ -4769,8 +4747,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigChunk &&chunk)
RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
{
cover("kernel.rtlil.sigspec.init.wire");
if (wire->width != 0) {
rep_ = CHUNK;
new (&chunk_) RTLIL::SigChunk(wire);
@ -4782,8 +4758,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
{
cover("kernel.rtlil.sigspec.init.wire_part");
if (width != 0) {
rep_ = CHUNK;
new (&chunk_) RTLIL::SigChunk(wire, offset, width);
@ -4795,8 +4769,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
RTLIL::SigSpec::SigSpec(const std::string &str)
{
cover("kernel.rtlil.sigspec.init.str");
if (str.size() != 0) {
rep_ = CHUNK;
new (&chunk_) RTLIL::SigChunk(str);
@ -4808,8 +4780,6 @@ RTLIL::SigSpec::SigSpec(const std::string &str)
RTLIL::SigSpec::SigSpec(int val, int width)
{
cover("kernel.rtlil.sigspec.init.int");
if (width != 0) {
rep_ = CHUNK;
new (&chunk_) RTLIL::SigChunk(val, width);
@ -4820,8 +4790,6 @@ RTLIL::SigSpec::SigSpec(int val, int width)
RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
{
cover("kernel.rtlil.sigspec.init.state");
if (width != 0) {
rep_ = CHUNK;
new (&chunk_) RTLIL::SigChunk(bit, width);
@ -4832,8 +4800,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
{
cover("kernel.rtlil.sigspec.init.bit");
if (width != 0) {
if (bit.wire == NULL) {
rep_ = CHUNK;
@ -4854,8 +4820,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
{
cover("kernel.rtlil.sigspec.init.stdvec_chunks");
init_empty_bits();
for (const auto &c : chunks)
append(c);
@ -4864,8 +4828,6 @@ RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
{
cover("kernel.rtlil.sigspec.init.stdvec_bits");
init_empty_bits();
for (const auto &bit : bits)
append(bit);
@ -4874,8 +4836,6 @@ RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> &bits)
{
cover("kernel.rtlil.sigspec.init.pool_bits");
init_empty_bits();
for (const auto &bit : bits)
append(bit);
@ -4884,8 +4844,6 @@ RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> &bits)
RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
{
cover("kernel.rtlil.sigspec.init.stdset_bits");
init_empty_bits();
for (const auto &bit : bits)
append(bit);
@ -4894,8 +4852,6 @@ RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
RTLIL::SigSpec::SigSpec(bool bit)
{
cover("kernel.rtlil.sigspec.init.bool");
rep_ = CHUNK;
new (&chunk_) RTLIL::SigChunk(bit ? RTLIL::S1 : RTLIL::S0);
check();
@ -4931,8 +4887,6 @@ void RTLIL::SigSpec::unpack()
if (rep_ == BITS)
return;
cover("kernel.rtlil.sigspec.convert.unpack");
std::vector<RTLIL::SigBit> bits;
bits.reserve(chunk_.width);
for (int i = 0; i < chunk_.width; i++)
@ -4948,8 +4902,6 @@ void RTLIL::SigSpec::try_repack()
if (rep_ != BITS)
return;
cover("kernel.rtlil.sigspec.convert.try_repack");
int bits_size = GetSize(bits_);
if (bits_size == 0)
return;
@ -4978,8 +4930,6 @@ void RTLIL::SigSpec::try_repack()
Hasher::hash_t RTLIL::SigSpec::updhash() const
{
cover("kernel.rtlil.sigspec.hash");
Hasher h;
for (auto &c : chunks())
if (c.wire == NULL) {
@ -5000,7 +4950,6 @@ Hasher::hash_t RTLIL::SigSpec::updhash() const
void RTLIL::SigSpec::sort()
{
unpack();
cover("kernel.rtlil.sigspec.sort");
std::sort(bits_.begin(), bits_.end());
hash_.clear();
try_repack();
@ -5009,8 +4958,6 @@ void RTLIL::SigSpec::sort()
void RTLIL::SigSpec::sort_and_unify()
{
unpack();
cover("kernel.rtlil.sigspec.sort_and_unify");
// A copy of the bits vector is used to prevent duplicating the logic from
// SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
// that isn't showing up as significant in profiles.
@ -5066,8 +5013,6 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
{
cover("kernel.rtlil.sigspec.replace_dict");
log_assert(other != NULL);
log_assert(size() == other->size());
@ -5095,8 +5040,6 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
{
cover("kernel.rtlil.sigspec.replace_map");
log_assert(other != NULL);
log_assert(size() == other->size());
@ -5130,11 +5073,6 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other
void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
{
if (other)
cover("kernel.rtlil.sigspec.remove_other");
else
cover("kernel.rtlil.sigspec.remove");
unpack();
if (other != NULL) {
log_assert(size() == other->size());
@ -5185,11 +5123,6 @@ void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *
void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
{
if (other)
cover("kernel.rtlil.sigspec.remove_other");
else
cover("kernel.rtlil.sigspec.remove");
unpack();
if (other != NULL) {
@ -5223,11 +5156,6 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec
void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
{
if (other)
cover("kernel.rtlil.sigspec.remove_other");
else
cover("kernel.rtlil.sigspec.remove");
unpack();
if (other != NULL) {
@ -5261,11 +5189,6 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other)
{
if (other)
cover("kernel.rtlil.sigspec.remove_other");
else
cover("kernel.rtlil.sigspec.remove");
unpack();
if (other != NULL) {
@ -5299,11 +5222,6 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *
RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
{
if (other)
cover("kernel.rtlil.sigspec.extract_other");
else
cover("kernel.rtlil.sigspec.extract");
log_assert(other == NULL || size() == other->size());
RTLIL::SigSpec ret;
@ -5337,11 +5255,6 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLI
RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
{
if (other)
cover("kernel.rtlil.sigspec.extract_other");
else
cover("kernel.rtlil.sigspec.extract");
log_assert(other == NULL || size() == other->size());
std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
@ -5367,8 +5280,6 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const
void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
{
cover("kernel.rtlil.sigspec.replace_pos");
if (with.size() == 0)
return;
@ -5393,8 +5304,6 @@ void RTLIL::SigSpec::remove_const()
{
if (rep_ == CHUNK)
{
cover("kernel.rtlil.sigspec.remove_const.packed");
if (chunk_.wire == NULL) {
chunk_.~SigChunk();
init_empty_bits();
@ -5403,8 +5312,6 @@ void RTLIL::SigSpec::remove_const()
}
else
{
cover("kernel.rtlil.sigspec.remove_const.unpacked");
std::vector<RTLIL::SigBit> new_bits;
new_bits.reserve(bits_.size());
for (auto &bit : bits_)
@ -5422,8 +5329,6 @@ void RTLIL::SigSpec::remove_const()
void RTLIL::SigSpec::remove(int offset, int length)
{
cover("kernel.rtlil.sigspec.remove_pos");
if (length == 0)
return;
@ -5446,8 +5351,6 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
log_assert(length >= 0);
log_assert(offset + length <= size());
cover("kernel.rtlil.sigspec.extract_pos");
SigSpec extracted;
Chunks cs = chunks();
auto it = cs.begin();
@ -5501,8 +5404,6 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
return;
}
cover("kernel.rtlil.sigspec.append");
hash_.clear();
if (rep_ == CHUNK && signal.rep_ == CHUNK && chunk_.wire == signal.chunk_.wire) {
if (chunk_.wire == NULL) {
@ -5534,8 +5435,6 @@ void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
}
if (rep_ == CHUNK && chunk_.wire == bit.wire) {
cover("kernel.rtlil.sigspec.append_bit.packed");
if (chunk_.wire == NULL) {
chunk_.data.push_back(bit.data);
chunk_.width++;
@ -5549,15 +5448,12 @@ void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
unpack();
cover("kernel.rtlil.sigspec.append_bit.unpacked");
bits_.push_back(bit);
check();
}
void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
{
cover("kernel.rtlil.sigspec.extend_u0");
if (size() > width)
remove(width, size() - width);
@ -5572,8 +5468,6 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
{
cover("kernel.rtlil.sigspec.repeat");
RTLIL::SigSpec sig;
for (int i = 0; i < num; i++)
sig.append(*this);
@ -5585,8 +5479,6 @@ void RTLIL::SigSpec::check(Module *mod) const
{
if (rep_ == CHUNK)
{
cover("kernel.rtlil.sigspec.check.packed");
log_assert(chunk_.width != 0);
if (chunk_.wire == NULL) {
log_assert(chunk_.offset == 0);
@ -5600,14 +5492,8 @@ void RTLIL::SigSpec::check(Module *mod) const
log_assert(chunk_.wire->module == mod);
}
}
else if (size() > 64)
else if (size() <= 64)
{
cover("kernel.rtlil.sigspec.check.skip");
}
else
{
cover("kernel.rtlil.sigspec.check.unpacked");
if (mod != nullptr) {
for (const RTLIL::SigBit &bit : bits_)
if (bit.wire != nullptr)
@ -5619,8 +5505,6 @@ void RTLIL::SigSpec::check(Module *mod) const
bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
{
cover("kernel.rtlil.sigspec.comp_lt");
if (this == &other)
return false;
@ -5634,14 +5518,11 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
++other_it;
}
cover("kernel.rtlil.sigspec.comp_lt.equal");
return false;
}
bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
{
cover("kernel.rtlil.sigspec.comp_eq");
if (this == &other)
return true;
@ -5655,14 +5536,11 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
++other_it;
}
cover("kernel.rtlil.sigspec.comp_eq.equal");
return true;
}
bool RTLIL::SigSpec::is_wire() const
{
cover("kernel.rtlil.sigspec.is_wire");
Chunks cs = chunks();
auto it = cs.begin();
if (it == cs.end())
@ -5673,8 +5551,6 @@ bool RTLIL::SigSpec::is_wire() const
bool RTLIL::SigSpec::is_chunk() const
{
cover("kernel.rtlil.sigspec.is_chunk");
Chunks cs = chunks();
auto it = cs.begin();
if (it == cs.end())
@ -5703,8 +5579,6 @@ bool RTLIL::SigSpec::known_driver() const
bool RTLIL::SigSpec::is_fully_const() const
{
cover("kernel.rtlil.sigspec.is_fully_const");
for (auto &chunk : chunks())
if (chunk.width > 0 && chunk.wire != NULL)
return false;
@ -5713,8 +5587,6 @@ bool RTLIL::SigSpec::is_fully_const() const
bool RTLIL::SigSpec::is_fully_zero() const
{
cover("kernel.rtlil.sigspec.is_fully_zero");
for (auto &chunk : chunks()) {
if (chunk.width > 0 && chunk.wire != NULL)
return false;
@ -5727,8 +5599,6 @@ bool RTLIL::SigSpec::is_fully_zero() const
bool RTLIL::SigSpec::is_fully_ones() const
{
cover("kernel.rtlil.sigspec.is_fully_ones");
for (auto &chunk : chunks()) {
if (chunk.width > 0 && chunk.wire != NULL)
return false;
@ -5741,8 +5611,6 @@ bool RTLIL::SigSpec::is_fully_ones() const
bool RTLIL::SigSpec::is_fully_def() const
{
cover("kernel.rtlil.sigspec.is_fully_def");
for (auto &chunk : chunks()) {
if (chunk.width > 0 && chunk.wire != NULL)
return false;
@ -5755,8 +5623,6 @@ bool RTLIL::SigSpec::is_fully_def() const
bool RTLIL::SigSpec::is_fully_undef() const
{
cover("kernel.rtlil.sigspec.is_fully_undef");
for (auto &chunk : chunks()) {
if (chunk.width > 0 && chunk.wire != NULL)
return false;
@ -5769,8 +5635,6 @@ bool RTLIL::SigSpec::is_fully_undef() const
bool RTLIL::SigSpec::has_const() const
{
cover("kernel.rtlil.sigspec.has_const");
for (auto &chunk : chunks())
if (chunk.width > 0 && chunk.wire == NULL)
return true;
@ -5779,8 +5643,6 @@ bool RTLIL::SigSpec::has_const() const
bool RTLIL::SigSpec::has_const(State state) const
{
cover("kernel.rtlil.sigspec.has_const");
for (auto &chunk : chunks())
if (chunk.width > 0 && chunk.wire == NULL && std::find(chunk.data.begin(), chunk.data.end(), state) != chunk.data.end())
return true;
@ -5790,8 +5652,6 @@ bool RTLIL::SigSpec::has_const(State state) const
bool RTLIL::SigSpec::has_marked_bits() const
{
cover("kernel.rtlil.sigspec.has_marked_bits");
for (auto &chunk : chunks())
if (chunk.width > 0 && chunk.wire == NULL) {
for (RTLIL::State d : chunk.data)
@ -5803,8 +5663,6 @@ bool RTLIL::SigSpec::has_marked_bits() const
bool RTLIL::SigSpec::is_onehot(int *pos) const
{
cover("kernel.rtlil.sigspec.is_onehot");
if (std::optional<RTLIL::Const> c = try_as_const())
return c->is_onehot(pos);
return false;
@ -5812,8 +5670,6 @@ bool RTLIL::SigSpec::is_onehot(int *pos) const
bool RTLIL::SigSpec::as_bool() const
{
cover("kernel.rtlil.sigspec.as_bool");
std::optional<RTLIL::Const> c = try_as_const();
log_assert(c.has_value());
return c->as_bool();
@ -5821,8 +5677,6 @@ bool RTLIL::SigSpec::as_bool() const
int RTLIL::SigSpec::as_int(bool is_signed) const
{
cover("kernel.rtlil.sigspec.as_int");
std::optional<RTLIL::Const> c = try_as_const();
log_assert(c.has_value());
return c->as_int(is_signed);
@ -5830,8 +5684,6 @@ int RTLIL::SigSpec::as_int(bool is_signed) const
bool RTLIL::SigSpec::convertible_to_int(bool is_signed) const
{
cover("kernel.rtlil.sigspec.convertible_to_int");
std::optional<RTLIL::Const> c = try_as_const();
if (!c.has_value())
return false;
@ -5840,8 +5692,6 @@ bool RTLIL::SigSpec::convertible_to_int(bool is_signed) const
std::optional<int> RTLIL::SigSpec::try_as_int(bool is_signed) const
{
cover("kernel.rtlil.sigspec.try_as_int");
std::optional<RTLIL::Const> c = try_as_const();
if (!c.has_value())
return std::nullopt;
@ -5850,8 +5700,6 @@ std::optional<int> RTLIL::SigSpec::try_as_int(bool is_signed) const
int RTLIL::SigSpec::as_int_saturating(bool is_signed) const
{
cover("kernel.rtlil.sigspec.try_as_int");
std::optional<RTLIL::Const> c = try_as_const();
log_assert(c.has_value());
return c->as_int_saturating(is_signed);
@ -5859,8 +5707,6 @@ int RTLIL::SigSpec::as_int_saturating(bool is_signed) const
std::string RTLIL::SigSpec::as_string() const
{
cover("kernel.rtlil.sigspec.as_string");
std::string str;
str.reserve(size());
std::vector<RTLIL::SigChunk> chunks = *this;
@ -5876,8 +5722,6 @@ std::string RTLIL::SigSpec::as_string() const
std::optional<RTLIL::Const> RTLIL::SigSpec::try_as_const() const
{
cover("kernel.rtlil.sigspec.as_const");
Chunks cs = chunks();
auto it = cs.begin();
if (it == cs.end())
@ -5890,8 +5734,6 @@ std::optional<RTLIL::Const> RTLIL::SigSpec::try_as_const() const
RTLIL::Const RTLIL::SigSpec::as_const() const
{
cover("kernel.rtlil.sigspec.as_const");
std::optional<RTLIL::Const> c = try_as_const();
log_assert(c.has_value());
return *c;
@ -5899,8 +5741,6 @@ RTLIL::Const RTLIL::SigSpec::as_const() const
RTLIL::Wire *RTLIL::SigSpec::as_wire() const
{
cover("kernel.rtlil.sigspec.as_wire");
Chunks cs = chunks();
auto it = cs.begin();
log_assert(it != cs.end());
@ -5911,8 +5751,6 @@ RTLIL::Wire *RTLIL::SigSpec::as_wire() const
RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
{
cover("kernel.rtlil.sigspec.as_chunk");
Chunks cs = chunks();
auto it = cs.begin();
log_assert(it != cs.end());
@ -5923,14 +5761,11 @@ RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
RTLIL::SigBit RTLIL::SigSpec::as_bit() const
{
cover("kernel.rtlil.sigspec.as_bit");
return RTLIL::SigBit(*this);
}
bool RTLIL::SigSpec::match(const char* pattern) const
{
cover("kernel.rtlil.sigspec.match");
int pattern_len = strlen(pattern);
log_assert(pattern_len == size());
@ -5960,8 +5795,6 @@ bool RTLIL::SigSpec::match(const char* pattern) const
std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
{
cover("kernel.rtlil.sigspec.to_sigbit_set");
std::set<RTLIL::SigBit> sigbits;
for (auto &c : chunks())
for (int i = 0; i < c.width; i++)
@ -5971,8 +5804,6 @@ std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
{
cover("kernel.rtlil.sigspec.to_sigbit_pool");
pool<RTLIL::SigBit> sigbits;
sigbits.reserve(size());
for (auto &c : chunks())
@ -5983,8 +5814,6 @@ pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
{
cover("kernel.rtlil.sigspec.to_sigbit_vector");
std::vector<RTLIL::SigBit> result;
result.reserve(size());
for (SigBit bit : *this)
@ -5994,8 +5823,6 @@ std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
{
cover("kernel.rtlil.sigspec.to_sigbit_map");
int this_size = size();
log_assert(this_size == other.size());
@ -6008,8 +5835,6 @@ std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL
dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
{
cover("kernel.rtlil.sigspec.to_sigbit_dict");
int this_size = size();
log_assert(this_size == other.size());
@ -6033,9 +5858,6 @@ static void sigspec_parse_split(std::vector<std::string> &tokens, const std::str
bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
{
cover("kernel.rtlil.sigspec.parse");
std::vector<std::string> tokens;
sigspec_parse_split(tokens, str, ',');
@ -6049,7 +5871,6 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
continue;
if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
cover("kernel.rtlil.sigspec.parse.const");
VERILOG_FRONTEND::ConstParser p{Location()};
auto ast = p.const2ast(netname);
if (ast == nullptr)
@ -6061,8 +5882,6 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
if (module == NULL)
return false;
cover("kernel.rtlil.sigspec.parse.net");
if (netname[0] != '$' && netname[0] != '\\')
netname = "\\" + netname;
@ -6091,13 +5910,11 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
std::vector<std::string> index_tokens;
sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
if (index_tokens.size() == 1) {
cover("kernel.rtlil.sigspec.parse.bit_sel");
int a = atoi(index_tokens.at(0).c_str());
if (a < 0 || a >= wire->width)
return false;
sig.append(RTLIL::SigSpec(wire, a));
} else {
cover("kernel.rtlil.sigspec.parse.part_sel");
int a = atoi(index_tokens.at(0).c_str());
int b = atoi(index_tokens.at(1).c_str());
if (a > b) {
@ -6122,8 +5939,6 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL
if (str.empty() || str[0] != '@')
return parse(sig, module, str);
cover("kernel.rtlil.sigspec.parse.sel");
str = RTLIL::escape_id(str.substr(1));
if (design->selection_vars.count(str) == 0)
return false;
@ -6140,13 +5955,11 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL
bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
{
if (str == "0") {
cover("kernel.rtlil.sigspec.parse.rhs_zeros");
sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.size());
return true;
}
if (str == "~0") {
cover("kernel.rtlil.sigspec.parse.rhs_ones");
sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.size());
return true;
}
@ -6156,7 +5969,6 @@ bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, R
long int val = strtol(p, &endptr, 10);
if (endptr && endptr != p && *endptr == 0) {
sig = RTLIL::SigSpec(val, lhs.size());
cover("kernel.rtlil.sigspec.parse.rhs_dec");
return true;
}
}

1
passes/cmds/Makefile.inc
View File

@ -27,7 +27,6 @@ OBJS += passes/cmds/logcmd.o
OBJS += passes/cmds/tee.o
OBJS += passes/cmds/write_file.o
OBJS += passes/cmds/connwrappers.o
OBJS += passes/cmds/cover.o
OBJS += passes/cmds/trace.o
OBJS += passes/cmds/plugin.o
OBJS += passes/cmds/check.o

163
passes/cmds/cover.cc
View File

@ -1,163 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2014 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/log_help.h"
#include <sys/types.h>
#ifndef _WIN32
# include <unistd.h>
#else
# include <io.h>
#endif
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct CoverPass : public Pass {
CoverPass() : Pass("cover", "print code coverage counters") {
internal();
}
bool formatted_help() override {
auto *help = PrettyHelp::get_current();
help->set_group("passes/status");
return false;
}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" cover [options] [pattern]\n");
log("\n");
log("Print the code coverage counters collected using the cover() macro in the Yosys\n");
log("C++ code. This is useful to figure out what parts of Yosys are utilized by a\n");
log("test bench.\n");
log("\n");
log(" -q\n");
log(" Do not print output to the normal destination (console and/or log file)\n");
log("\n");
log(" -o file\n");
log(" Write output to this file, truncate if exists.\n");
log("\n");
log(" -a file\n");
log(" Write output to this file, append if exists.\n");
log("\n");
log(" -d dir\n");
log(" Write output to a newly created file in the specified directory.\n");
log("\n");
log("When one or more pattern (shell wildcards) are specified, then only counters\n");
log("matching at least one pattern are printed.\n");
log("\n");
log("\n");
log("It is also possible to instruct Yosys to print the coverage counters on program\n");
log("exit to a file using environment variables:\n");
log("\n");
log(" YOSYS_COVER_DIR=\"{dir-name}\" yosys {args}\n");
log("\n");
log(" This will create a file (with an auto-generated name) in this\n");
log(" directory and write the coverage counters to it.\n");
log("\n");
log(" YOSYS_COVER_FILE=\"{file-name}\" yosys {args}\n");
log("\n");
log(" This will append the coverage counters to the specified file.\n");
log("\n");
log("\n");
log("Hint: Use the following AWK command to consolidate Yosys coverage files:\n");
log("\n");
log(" gawk '{ p[$3] = $1; c[$3] += $2; } END { for (i in p)\n");
log(" printf \"%%-60s %%10d %%s\\n\", p[i], c[i], i; }' {files} | sort -k3\n");
log("\n");
log("\n");
log("Coverage counters are only available in Yosys for Linux.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<FILE*> out_files;
std::vector<std::string> patterns;
bool do_log = true;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-q") {
do_log = false;
continue;
}
if ((args[argidx] == "-o" || args[argidx] == "-a" || args[argidx] == "-d") && argidx+1 < args.size()) {
const char *open_mode = args[argidx] == "-a" ? "a+" : "w";
const std::string &filename = args[++argidx];
FILE *f = nullptr;
if (args[argidx-1] == "-d") {
#if defined(_WIN32) || defined(__wasm)
log_cmd_error("The 'cover -d' option is not supported on this platform.\n");
#else
char filename_buffer[4096];
snprintf(filename_buffer, 4096, "%s/yosys_cover_%d_XXXXXX.txt", filename.c_str(), getpid());
f = fdopen(mkstemps(filename_buffer, 4), "w");
#endif
} else {
f = fopen(filename.c_str(), open_mode);
}
if (f == NULL) {
for (auto f : out_files)
fclose(f);
log_cmd_error("Can't create file %s%s.\n", args[argidx-1] == "-d" ? "in directory " : "", args[argidx]);
}
out_files.push_back(f);
continue;
}
break;
}
while (argidx < args.size() && args[argidx].compare(0, 1, "-") != 0)
patterns.push_back(args[argidx++]);
extra_args(args, argidx, design);
if (do_log) {
log_header(design, "Printing code coverage counters.\n");
log("\n");
}
#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))
for (auto &it : get_coverage_data()) {
if (!patterns.empty()) {
for (auto &p : patterns)
if (patmatch(p.c_str(), it.first.c_str()))
goto pattern_match;
continue;
}
pattern_match:
for (auto f : out_files)
fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str());
if (do_log)
log("%-60s %10d %s\n", it.second.first, it.second.second, it.first);
}
#else
for (auto f : out_files)
fclose(f);
log_cmd_error("This version of Yosys was not built with support for code coverage counters.\n");
#endif
for (auto f : out_files)
fclose(f);
}
} CoverPass;
PRIVATE_NAMESPACE_END

69
passes/opt/opt_expr.cc
View File

@ -300,8 +300,6 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
log_debug("\n");
}
cover_list("opt.opt_expr.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str());
module->remove(cell);
did_something = true;
return true;
@ -523,7 +521,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
for (auto cell : cells.sorted)
{
#define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
#define ACTION_DO(_p_, _s_) do { replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
#define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))
bool detect_const_and = false;
@ -570,19 +568,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (detect_const_and && (found_zero || found_inv || (found_undef && consume_x))) {
cover("opt.opt_expr.const_and");
replace_cell(assign_map, module, cell, "const_and", ID::Y, RTLIL::State::S0);
goto next_cell;
}
if (detect_const_or && (found_one || found_inv || (found_undef && consume_x))) {
cover("opt.opt_expr.const_or");
replace_cell(assign_map, module, cell, "const_or", ID::Y, RTLIL::State::S1);
goto next_cell;
}
if (non_const_input != State::Sm && !found_undef) {
cover("opt.opt_expr.and_or_buffer");
replace_cell(assign_map, module, cell, "and_or_buffer", ID::Y, non_const_input);
goto next_cell;
}
@ -594,12 +589,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
SigBit sig_b = assign_map(cell->getPort(ID::B));
if (!keepdc && (sig_a == sig_b || sig_a == State::Sx || sig_a == State::Sz || sig_b == State::Sx || sig_b == State::Sz)) {
if (cell->type.in(ID($xor), ID($_XOR_))) {
cover("opt.opt_expr.const_xor");
replace_cell(assign_map, module, cell, "const_xor", ID::Y, RTLIL::State::S0);
goto next_cell;
}
if (cell->type.in(ID($xnor), ID($_XNOR_))) {
cover("opt.opt_expr.const_xnor");
// For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_
int width = GetSize(cell->getPort(ID::Y));
replace_cell(assign_map, module, cell, "const_xnor", ID::Y, SigSpec(RTLIL::State::S1, width));
@ -612,7 +605,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
std::swap(sig_a, sig_b);
if (sig_b == State::S0 || sig_b == State::S1) {
if (cell->type.in(ID($xor), ID($_XOR_))) {
cover("opt.opt_expr.xor_buffer");
SigSpec sig_y;
if (cell->type == ID($xor))
sig_y = (sig_b == State::S1 ? module->Not(NEW_ID2_SUFFIX("xor_inv"), sig_a, false, cell->get_src_attribute()).as_bit() : sig_a); // SILIMATE: Improve the naming
@ -623,7 +615,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
goto next_cell;
}
if (cell->type.in(ID($xnor), ID($_XNOR_))) {
cover("opt.opt_expr.xnor_buffer");
SigSpec sig_y;
if (cell->type == ID($xnor)) {
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID2_SUFFIX("xnor_inv"), sig_a, false, cell->get_src_attribute()).as_bit()); // SILIMATE: Improve the naming
@ -644,13 +635,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
{
if (cell->type == ID($reduce_xnor)) {
cover("opt.opt_expr.reduce_xnor_not");
log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type = ID($not);
did_something = true;
} else {
cover("opt.opt_expr.unary_buffer");
replace_cell(assign_map, module, cell, "unary_buffer", ID::Y, cell->getPort(ID::A));
}
goto next_cell;
@ -666,7 +655,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (a_fully_const != b_fully_const)
{
cover("opt.opt_expr.bitwise_logic_one_const");
log_debug("Replacing %s cell `%s' in module `%s' having one fully constant input\n",
log_id(cell->type), log_id(cell->name), log_id(module));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
@ -833,7 +821,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
new_sig_a.append(neutral_bit);
if (GetSize(new_sig_a) < GetSize(sig_a)) {
cover_list("opt.opt_expr.fine.neutral_A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_and", "$reduce_bool", cell->type.str());
log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a));
cell->setPort(ID::A, new_sig_a);
@ -856,7 +843,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
new_sig_b.append(neutral_bit);
if (GetSize(new_sig_b) < GetSize(sig_b)) {
cover_list("opt.opt_expr.fine.neutral_B", "$logic_and", "$logic_or", cell->type.str());
log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b));
cell->setPort(ID::B, new_sig_b);
@ -882,7 +868,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) {
cover("opt.opt_expr.fine.$reduce_and");
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a);
@ -908,7 +893,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) {
cover_list("opt.opt_expr.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type.str());
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a);
@ -934,7 +918,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) {
cover_list("opt.opt_expr.fine.B", "$logic_and", "$logic_or", cell->type.str());
log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
cell->setPort(ID::B, sig_b = new_b);
@ -969,7 +952,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
break;
}
if (i > 0) {
cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
SigSpec new_a = sig_a.extract_end(i);
SigSpec new_b = sig_b.extract_end(i);
@ -1026,7 +1008,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
break;
}
if (i > 0) {
cover("opt.opt_expr.fine.$alu");
log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
SigSpec new_a = sig_a.extract_end(i);
SigSpec new_b = sig_b.extract_end(i);
@ -1065,8 +1046,6 @@ skip_fine_alu:
if (0) {
found_the_x_bit:
cover_list("opt.opt_expr.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
"$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$divfloor", "$modfloor", "$pow", cell->type.str());
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($lt), ID($le), ID($ge), ID($gt)))
replace_cell(assign_map, module, cell, "x-bit in input", ID::Y, RTLIL::State::Sx);
else
@ -1088,7 +1067,6 @@ skip_fine_alu:
}
if (width < GetSize(sig_a)) {
cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str());
sig_a.remove(width, GetSize(sig_a)-width);
cell->setPort(ID::A, sig_a);
cell->setParam(ID::A_WIDTH, width);
@ -1099,13 +1077,11 @@ skip_fine_alu:
if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && GetSize(cell->getPort(ID::Y)) == 1 &&
invert_map.count(assign_map(cell->getPort(ID::A))) != 0) {
cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());
replace_cell(assign_map, module, cell, "double_invert", ID::Y, invert_map.at(assign_map(cell->getPort(ID::A))));
goto next_cell;
}
if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID::S))) != 0) {
cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str());
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
RTLIL::SigSpec tmp = cell->getPort(ID::A);
cell->setPort(ID::A, cell->getPort(ID::B));
@ -1188,7 +1164,6 @@ skip_fine_alu:
if (input.match(" 1")) ACTION_DO(ID::Y, input.extract(1, 1));
if (input.match("01 ")) ACTION_DO(ID::Y, input.extract(0, 1));
if (input.match("10 ")) {
cover("opt.opt_expr.mux_to_inv");
cell->type = ID($_NOT_);
cell->setPort(ID::A, input.extract(0, 1));
cell->unsetPort(ID::B);
@ -1215,7 +1190,6 @@ skip_fine_alu:
if (input == State::S1)
ACTION_DO(ID::Y, cell->getPort(ID::A));
if (input == State::S0 && !a.is_fully_undef()) {
cover("opt.opt_expr.action_" S__LINE__);
log_debug("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str());
cell->setPort(ID::A, SigSpec(State::Sx, GetSize(a)));
@ -1240,7 +1214,6 @@ skip_fine_alu:
log_assert(GetSize(a) == GetSize(b));
for (int i = 0; i < GetSize(a); i++) {
if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1);
new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y);
@ -1253,7 +1226,6 @@ skip_fine_alu:
}
if (new_a.size() == 0) {
cover_list("opt.opt_expr.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S1 : RTLIL::State::S0);
new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
replace_cell(assign_map, module, cell, "empty", ID::Y, new_y);
@ -1261,7 +1233,6 @@ skip_fine_alu:
}
if (new_a.size() < a.size() || new_b.size() < b.size()) {
cover_list("opt.opt_expr.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b);
cell->parameters[ID::A_WIDTH] = new_a.size();
@ -1276,7 +1247,6 @@ skip_fine_alu:
RTLIL::SigSpec b = assign_map(cell->getPort(ID::B));
if (a.is_fully_const() && !b.is_fully_const()) {
cover_list("opt.opt_expr.eqneq.swapconst", "$eq", "$ne", cell->type.str());
cell->setPort(ID::A, b);
cell->setPort(ID::B, a);
std::swap(a, b);
@ -1291,7 +1261,6 @@ skip_fine_alu:
RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, cell->getPort(ID::A));
} else {
cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->type = ID($not);
cell->parameters.erase(ID::B_WIDTH);
@ -1306,7 +1275,6 @@ skip_fine_alu:
if (cell->type.in(ID($eq), ID($ne)) &&
(assign_map(cell->getPort(ID::A)).is_fully_zero() || assign_map(cell->getPort(ID::B)).is_fully_zero()))
{
cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
@ -1354,8 +1322,6 @@ skip_fine_alu:
sig_y[i] = sig_a[GetSize(sig_a)-1];
}
cover_list("opt.opt_expr.constshift", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", cell->type.str());
log_debug("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n",
log_id(cell->type), log_id(cell), log_signal(assign_map(cell->getPort(ID::B))), shift_bits, log_id(module), log_signal(sig_y));
@ -1428,11 +1394,6 @@ skip_fine_alu:
if (identity_wrt_a || identity_wrt_b)
{
if (identity_wrt_a)
cover_list("opt.opt_expr.identwrt.a", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
if (identity_wrt_b)
cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
@ -1481,14 +1442,12 @@ skip_identity:
if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == State::S0 && cell->getPort(ID::B) == State::S1) {
cover_list("opt.opt_expr.mux_bool", "$mux", "$_MUX_", cell->type.str());
replace_cell(assign_map, module, cell, "mux_bool", ID::Y, cell->getPort(ID::S));
goto next_cell;
}
if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == State::S1 && cell->getPort(ID::B) == State::S0) {
cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::B);
@ -1507,7 +1466,6 @@ skip_identity:
}
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0) {
cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::S);
@ -1548,7 +1506,6 @@ skip_identity:
}
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::B) == State::S1) {
cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::B, cell->getPort(ID::S));
cell->unsetPort(ID::S);
@ -1593,7 +1550,6 @@ skip_identity:
int width = GetSize(cell->getPort(ID::A));
if ((cell->getPort(ID::A).is_fully_undef() && cell->getPort(ID::B).is_fully_undef()) ||
cell->getPort(ID::S).is_fully_undef()) {
cover_list("opt.opt_expr.mux_undef", "$mux", "$pmux", cell->type.str());
replace_cell(assign_map, module, cell, "mux_undef", ID::Y, cell->getPort(ID::A));
goto next_cell;
}
@ -1612,17 +1568,14 @@ skip_identity:
new_s = new_s.extract(0, new_s.size()-1);
}
if (new_s.size() == 0) {
cover_list("opt.opt_expr.mux_empty", "$mux", "$pmux", cell->type.str());
replace_cell(assign_map, module, cell, "mux_empty", ID::Y, new_a);
goto next_cell;
}
if (new_a == RTLIL::SigSpec(RTLIL::State::S0) && new_b == RTLIL::SigSpec(RTLIL::State::S1)) {
cover_list("opt.opt_expr.mux_sel01", "$mux", "$pmux", cell->type.str());
replace_cell(assign_map, module, cell, "mux_sel01", ID::Y, new_s);
goto next_cell;
}
if (cell->getPort(ID::S).size() != new_s.size()) {
cover_list("opt.opt_expr.mux_reduce", "$mux", "$pmux", cell->type.str());
log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
GetSize(cell->getPort(ID::S)) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::A, new_a);
@ -1662,7 +1615,6 @@ skip_identity:
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \
cell->parameters[ID::A_SIGNED].as_bool(), false, \
cell->parameters[ID::Y_WIDTH].as_int())); \
cover("opt.opt_expr.const.$" #_t); \
replace_cell(assign_map, module, cell, stringf("%s", log_signal(a)), ID::Y, y); \
goto next_cell; \
} \
@ -1677,7 +1629,6 @@ skip_identity:
cell->parameters[ID::A_SIGNED].as_bool(), \
cell->parameters[ID::B_SIGNED].as_bool(), \
cell->parameters[ID::Y_WIDTH].as_int())); \
cover("opt.opt_expr.const.$" #_t); \
replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \
goto next_cell; \
} \
@ -1689,7 +1640,6 @@ skip_identity:
assign_map.apply(a), assign_map.apply(b); \
if (a.is_fully_const() && b.is_fully_const()) { \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const())); \
cover("opt.opt_expr.const.$" #_t); \
replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \
goto next_cell; \
} \
@ -1702,7 +1652,6 @@ skip_identity:
assign_map.apply(a), assign_map.apply(b), assign_map.apply(s); \
if (a.is_fully_const() && b.is_fully_const() && s.is_fully_const()) { \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), s.as_const())); \
cover("opt.opt_expr.const.$" #_t); \
replace_cell(assign_map, module, cell, stringf("%s, %s, %s", log_signal(a), log_signal(b), log_signal(s)), ID::Y, y); \
goto next_cell; \
} \
@ -1819,8 +1768,6 @@ skip_identity:
{
if (sig_a.is_fully_zero())
{
cover("opt.opt_expr.mul_shift.zero");
log_debug("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
cell->name.c_str(), module->name.c_str());
@ -1834,11 +1781,6 @@ skip_identity:
int exp;
if (sig_a.is_onehot(&exp) && !(a_signed && exp == GetSize(sig_a) - 1))
{
if (swapped_ab)
cover("opt.opt_expr.mul_shift.swapped");
else
cover("opt.opt_expr.mul_shift.unswapped");
log_debug("Replacing multiply-by-%s cell `%s' in module `%s' with shift-by-%d.\n",
log_signal(sig_a), cell->name.c_str(), module->name.c_str(), exp);
@ -1872,8 +1814,6 @@ skip_identity:
break;
if (a_zeros || b_zeros) {
int y_zeros = a_zeros + b_zeros;
cover("opt.opt_expr.mul_low_zeros");
log_debug("Removing low %d A and %d B bits from cell `%s' in module `%s'.\n",
a_zeros, b_zeros, cell->name.c_str(), module->name.c_str());
@ -1915,8 +1855,6 @@ skip_identity:
{
if (sig_b.is_fully_zero())
{
cover("opt.opt_expr.divmod_zero");
log_debug("Replacing divide-by-zero cell `%s' in module `%s' with undef-driver.\n",
cell->name.c_str(), module->name.c_str());
@ -1932,8 +1870,6 @@ skip_identity:
{
if (cell->type.in(ID($div), ID($divfloor)))
{
cover("opt.opt_expr.div_shift");
bool is_truncating = cell->type == ID($div);
log_debug("Replacing %s-divide-by-%s cell `%s' in module `%s' with shift-by-%d.\n",
is_truncating ? "truncating" : "flooring",
@ -1962,8 +1898,6 @@ skip_identity:
}
else if (cell->type.in(ID($mod), ID($modfloor)))
{
cover("opt.opt_expr.mod_mask");
bool is_truncating = cell->type == ID($mod);
log_debug("Replacing %s-modulo-by-%s cell `%s' in module `%s' with bitmask.\n",
is_truncating ? "truncating" : "flooring",
@ -2093,7 +2027,6 @@ skip_identity:
sig_ci = p.second;
}
cover("opt.opt_expr.alu_split");
module->remove(cell);
did_something = true;

28
tests/techmap/abc_speed_gia_only.script Normal file
View File

@ -0,0 +1,28 @@
&st
&dch -r
&nf
&st
&syn2
&if -g -K 6
&synch2 -r
&nf
&st
&syn2
&if -g -K 6
&synch2 -r
&nf
&st
&syn2
&if -g -K 6
&synch2 -r
&nf
&st
&syn2
&if -g -K 6
&synch2 -r
&nf
&st
&syn2
&if -g -K 6
&synch2 -r
&nf

60
tests/techmap/xaiger2-5169.ys Normal file
View File

@ -0,0 +1,60 @@
read_rtlil <<EOF
# Generated by Yosys 0.53+98 (git sha1 780b12271, g++ 15.1.1 -fPIC -O3)
autoidx 30
attribute \top 1
attribute \src "top.v:1.1-21.10"
module \top
attribute \src "top.v:7.15-7.18"
wire output 1 \led
attribute \src "top.v:9.8-9.9"
wire \w
attribute \src "top.v:20.16-20.18"
cell $not $not$top.v:20$1
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \w
connect \Y \led
end
attribute \module_not_derived 1
attribute \src "top.v:10.10-18.4"
cell \CC_MX4 \mux
connect \D0 1'x
connect \D1 1'x
connect \D2 1'x
connect \D3 { }
connect \S0 1'x
connect \S1 1'x
connect \Y \w
end
end
EOF
read_verilog -lib -specify <<EOF
(* abc9_box, lib_whitebox *)
module CC_MX4 (
input D0, D1, D2, D3,
input S0, S1,
output Y
);
specify
(D0 => Y) = 453;
(D1 => Y) = 449;
(D2 => Y) = 488;
(D3 => Y) = 484;
(S0 => Y) = 422;
(S1 => Y) = 385;
endspecify
assign Y = S1 ? (S0 ? D3 : D2) :
(S0 ? D1 : D0);
endmodule
EOF
logger -expect error "Malformed design" 1
abc_new -script abc_speed_gia_only.script -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib