mirror of https://github.com/YosysHQ/yosys.git
Fix wreduce speed more
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parent
f7dbfcb278
commit
ae2ed5e82a
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@ -78,6 +78,7 @@ struct ModIndex : public RTLIL::Monitor
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SigMap sigmap;
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RTLIL::Module *module;
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std::map<RTLIL::SigBit, SigBitInfo> database;
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int reload_counter;
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int auto_reload_counter;
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bool auto_reload_module;
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@ -106,6 +107,10 @@ struct ModIndex : public RTLIL::Monitor
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void reload_module(bool reset_sigmap = true)
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{
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reload_counter++;
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if (reload_counter % 10 == 0)
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log_warning("ModIndex::reload_module() called %d times.\n", reload_counter);
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if (reset_sigmap) {
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sigmap.clear();
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sigmap.set(module);
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@ -231,6 +236,7 @@ struct ModIndex : public RTLIL::Monitor
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ModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)
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{
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reload_counter = 0;
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auto_reload_counter = 0;
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auto_reload_module = true;
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module->monitors.insert(this);
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@ -78,6 +78,8 @@ struct WreduceWorker
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for (int i = GetSize(sig_y)-1; i >= 0; i--)
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{
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auto info = mi.query(sig_y[i]);
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if (info == nullptr)
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return;
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if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_y[i]))) {
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bits_removed.push_back(State::Sx);
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continue;
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@ -408,6 +410,8 @@ struct WreduceWorker
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break;
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auto info = mi.query(bit);
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if (info == nullptr)
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return;
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if (info->is_output || GetSize(info->ports) > 1)
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break;
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@ -566,6 +570,10 @@ struct WreduceWorker
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for (int i = GetSize(w)-1; i >= 0; i--) {
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SigBit bit(w, i);
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auto info = mi.query(bit);
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if (info == nullptr) {
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unused_top_bits = 0;
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break;
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}
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if (info && (info->is_input || info->is_output || GetSize(info->ports) > 0))
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break;
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unused_top_bits++;
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