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2633 Commits

Author SHA1 Message Date
Krystine Sherwin 0360a4bd0a
tests/check_mem: Drop unused init check 
It was also raising an error in `read_verilog`.
 2026-05-30 11:06:11 +12:00
Emil J. Tywoniak 80bdbaa010 genrtlil: don't avoid emitting flops for nosync 2026-05-29 11:37:08 +02:00
Krystine Sherwin 52e0030cc5
tests/check_mem: Add problematic case 
Verific reports it as 16 2-bit addresses, meaning we have to iterate over the last dimension while skipping indices.
 2026-05-29 18:40:25 +12:00
Krystine Sherwin ab5f25db9a
Add test for non-contiguous memory init 
Also negative memory addresses.
 2026-05-29 18:40:24 +12:00
Krystine Sherwin aac7366862
tests: Add check_mem to vanilla-test 2026-05-29 18:40:24 +12:00
Krystine Sherwin f6327cc444
check_mem: Add -non-const option 
Can identify potentially dangerous addressing, but also prone to false-positives.
 2026-05-29 18:40:24 +12:00
Krystine Sherwin 07e3d648aa
Add check_mem command 
Comes with a set of tests which (currently) pass with `read_verilog` but fail with `verific` based on #5878.
Add `--check-sv`, an alternative to `--prove-sv` with generator defined yosys commands.  Helpful for when you want to run the same set of commands on a bunch of sv files.
 2026-05-29 18:40:23 +12:00
Miodrag Milanović 1801abf30a
Merge pull request #5913 from YosysHQ/abcexternal 
Putting back some Makefile.conf
 2026-05-28 09:49:16 +00:00
Miodrag Milanovic d8587f44f0 Putting back some Makefile.conf 2026-05-28 11:13:29 +02:00
nella d6106f141c Add matching for fused mac operations for Nexus (fix #5906). 2026-05-28 09:58:18 +02:00
junyao 6f111118de proc: ignore nosync temporaries in always_latch checks 2026-05-26 00:56:07 +08:00
nella 68df0be7d2 Remove eqbits flag. 2026-05-25 14:16:55 +02:00
nella 04a1611346 Tests. 2026-05-20 16:44:52 +02:00
nella d85e3f10de Add tests. 2026-05-20 16:44:52 +02:00
Miodrag Milanovic 4c8e61a52b Expose SBY binary location 2026-05-19 16:08:21 +02:00
Miodrag Milanovic 07924a3c62 Use common.mk for sva tests as well 2026-05-19 15:15:41 +02:00
Miodrag Milanovic 2b3f4c37f5 Fix functional tests 2026-05-19 14:42:08 +02:00
Miodrag Milanovic 15e09163cd Do not use Makefile.conf 2026-05-19 14:29:06 +02:00
Miodrag Milanovic c0779f488a Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
nella 886d0a7043
Merge branch 'main' into gus/sim-with-vcd-tuneup 2026-05-19 12:17:29 +02:00
Emil J. Tywoniak 1c831aa50d threading: whitespace 2026-05-18 16:26:14 +02:00
Miodrag Milanovic 4a4c3a3be6 Make better validation 2026-05-18 08:50:38 +02:00
Miodrag Milanovic ef092e1f15 Include conf so individual test running works 2026-05-18 08:50:20 +02:00
Leon White 59c1bc35cb Fix aiger tests when ABCEXTERNAL is set 2026-05-16 09:12:20 +02:00
nella 38c2806636 Make sure to apply correct signedness to loop vars. 2026-05-13 16:52:07 +02:00
nella 7d3e56523b Preserve param signedness across overrides. 2026-05-13 16:25:15 +02:00
Miodrag Milanovic 1ef6311e5b Update documentation and few more defines 2026-05-13 11:24:45 +02:00
Miodrag Milanovic 7fe32137bd Revert "Fix tests due to ABC improvements" 
This reverts commit 417e871b06.
 2026-05-11 14:47:08 +02:00
Emil J 1f02343268
Merge pull request #5817 from YosysHQ/emil/clockgate-reject-sdffe 
clockgate: reject $sdffe to fix priority handling
 2026-05-08 18:38:51 +00:00
Emil J. Tywoniak 425d47ad2c clockgate: test $sdffe rejected 2026-05-07 16:13:14 +02:00
Emil J. Tywoniak 687e5442f2 clockgate: formal liberty tests 2026-05-07 16:08:55 +02:00
Emil J 4e35ed5955
Merge pull request #5827 from cdleary/cdleary/2026-04-21-sv-positional-assignment-unpacked 
Support positional assignment patterns for unpacked arrays
 2026-05-07 10:55:17 +00:00
Lofty ab316c14d2
Merge pull request #5844 from YosysHQ/lofty/abc-refactor-5 
abc_new: integration testing via synth_gatemate
 2026-05-06 13:40:15 +00:00
Lofty fecea911ff synth_gatemate: add -abc_new option 2026-05-06 14:02:48 +01:00
Lofty 0d3923d086 abc_new: use default script if not specified 2026-04-28 12:33:21 +01:00
Emil J a966d06524
Merge pull request #5825 from petterreinholdtsen/autotest-race-text-busy 
Added locking around compiling in autotest.sh to avoid text busy race.
 2026-04-28 09:12:33 +00:00
Emil J cfa66f5335
Merge pull request #5824 from petterreinholdtsen/autotest-cxxflags 
Use CPPFLAGS and CXXFLAGS when compiling in autotest.sh.
 2026-04-27 22:06:07 +00:00
Petter Reinholdtsen 3187275184 Use CPPFLAGS and CXXFLAGS when compiling in autotest.sh. 
This ensure the build flags used elsewhere are included
also during testing.

Patch based on change from Daniel Gröber via Debian.

See also issue #5805.
 2026-04-25 06:47:26 +02:00
Petter Reinholdtsen 59b3b6d4e4 Added locking around compiling in autotest.sh to avoid text busy race. 
Patch by Daniel Gröber via Debian.

See also issue #5805.
 2026-04-25 00:01:34 +02:00
Petter Reinholdtsen c5a8c3cca5 Made autotest.sh print log on error for easier debugging in CI setups. 
Patch by Daniel Gröber via Debian.

See also issue #5805.
 2026-04-25 00:01:03 +02:00
Emil J ec0a102302
Merge pull request #5832 from YosysHQ/emil/simple-extract 
rtlil: rewrite SigSpec::extract for perf and packing
 2026-04-24 19:03:53 +00:00
Emil J. Tywoniak 10bbda93f7 rtlil: extend SigSpec::extract test 2026-04-24 11:04:19 +02:00
Emil J. Tywoniak a2dafce910 unit tests: rename SigSpec::extract test 2026-04-24 11:04:19 +02:00
Emil J. Tywoniak 25b9b796c4 rtlil: complicate extract again for packing 2026-04-24 11:04:19 +02:00
Christopher D. Leary 390f09b89a Support positional assignment patterns for unpacked arrays 2026-04-23 14:29:38 -07:00
Emil J 2dc69a7578
Merge pull request #5828 from YosysHQ/emil/bash-no-fhs 
Remove FHS dependency by replacing /bin/bash with /usr/bin/env bash
 2026-04-23 15:47:57 +00:00
Emil J. Tywoniak 14d0138d0c Remove FHS dependency by replacing /bin/sh with /usr/bin/env sh 2026-04-23 15:55:11 +02:00
Emil J 64e7ce2f57
Merge pull request #5803 from YosysHQ/emil/specrule-port-sanity 
Fix $specrule port naming inconsistency
 2026-04-22 10:46:36 +00:00
Emil J. Tywoniak f213a34427 Remove FHS dependency by replacing /bin/bash with /usr/bin/env bash everywhere 2026-04-22 10:39:19 +02:00
Miodrag Milanovic a666712687 Update arith_tree tests 2026-04-16 11:04:14 +02:00
Miodrag Milanovic 5737d2db35 Cleanup 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 76732497b9 Cleanup 2026-04-16 11:00:44 +02:00
Miodrag Milanovic bfd3e150fa Add proper deps 2026-04-16 11:00:44 +02:00
Miodrag Milanovic f04532bbac Try to make it more stable 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 8bed9bd824 Use this for now so we can see actual output of functional tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic a490f1c3c4 Move output redirect to one place 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 9c3d79b041 Cleanup 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 1aad357370 Fix some escaping with different approach 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 5ffa0b1dd7 Disabled some in fmt for now 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 686267ea81 Convert functional 2026-04-16 11:00:44 +02:00
Miodrag Milanovic bfd639f6a0 Disable failing test for now 2026-04-16 11:00:44 +02:00
Miodrag Milanovic f087a94470 Convert svinterfaces 2026-04-16 11:00:44 +02:00
Miodrag Milanovic f42800d4d3 Convert arch 2026-04-16 11:00:44 +02:00
Miodrag Milanovic c272bfbdc3 Convert liberty 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 149e2f343a Converted cxxrtl 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 4a89ae66ff Small fix 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 1c76cadac7 Converted rpc 2026-04-16 11:00:44 +02:00
Miodrag Milanovic fdccbe584d Convert realmath 2026-04-16 11:00:44 +02:00
nella 3ceeb3b00c Consolidated memlib generate script 2026-04-16 11:00:44 +02:00
nella 58e0473e29 Convert bram tests 2026-04-16 11:00:44 +02:00
nella ee31950770 Convert memfile tests 2026-04-16 11:00:44 +02:00
nella 4a9dc33098 Convert memlib tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 1effec2029 Make test simple 2026-04-16 11:00:44 +02:00
Miodrag Milanovic c15bcca25a Better fix 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 0ba9a0fb16 Try fixing tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic d1dc23d9f8 Did share, opt_share and fsm 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 652bbd2b41 Convert xprop tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 68e01a03d7 Converted some more 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 2bc46e77c8 Converted blif tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 1231bd5397 Convert memories tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 5a06a79c0c Correctly handle errors 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 2a8d369be3 Document not covered 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 1bfb95513c Convert autotest script wrapper 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 474d0d7b2e cleanup 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 8953007483 Use generic testing on few more places 2026-04-16 11:00:44 +02:00
Miodrag Milanovic f96fa5ff00 cleanup 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 8ff28a2a86 add prep 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 336a06d091 Add common.mk 2026-04-16 11:00:44 +02:00
Miodrag Milanovic c04d724337 report on summary 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 45bb0413bf Look for all result files 2026-04-16 11:00:44 +02:00
Miodrag Milanovic b361569abf Save results, and create summary and report 2026-04-16 11:00:44 +02:00
Miodrag Milanovic ced2521b03 Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
Miodrag Milanovic a2e1fbcfc6 Enabled realmath that was disabled for some reason 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 2f9e35acb8 Fix deprecation warning 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 712ce93501 Clean some seed-tests outputs 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 999255e40c Clean some seed-tests outputs 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 2774671346 Cleanup for abcopt-tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic fc55f16fae Ignore some generated files 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 3c2adfb523 Do not write to console for makefile-tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 8f7e5e9449 Make sure targets are built for tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 5494000fd7 Move clean for tests in proper Makefile 2026-04-16 11:00:44 +02:00
Miodrag Milanovic c99855535a Split vanilla-test to separate Makefile 2026-04-16 11:00:44 +02:00
Emil J. Tywoniak 3e45f9729e fix $specrule port naming 2026-04-13 22:34:46 +02:00
nella fc71719e6e Rename csa_tree to arith_tree. 2026-04-13 12:48:05 +02:00
nella c3c577f333 Fix test cases. 2026-04-13 12:48:05 +02:00
nella 42c309347b Clarify. 2026-04-13 12:48:05 +02:00
nella 4f4c820f73 Cleaned up CSA tests. 2026-04-13 12:48:05 +02:00
nella 9cc2e7d95e rm misc comments. 2026-04-13 12:48:05 +02:00
nella 9dc408eea7 CSA add alumacc related tests. 2026-04-13 12:48:05 +02:00
nella fc9adae9a2 Consolidate csa tests. 2026-04-13 12:48:05 +02:00
nella ab1c423692 Tighten csa tests. 2026-04-13 12:48:05 +02:00
nella cfee6bb4af Add more robsutness tests. 2026-04-13 12:48:05 +02:00
nella 6b0caedcdd Add chain tests and tighten synthesis assertions for csa. 2026-04-13 12:48:05 +02:00
nella 7183016910 Edge case tests. 2026-04-13 12:48:05 +02:00
nella 1a4a41812c Add csa synth tests. 2026-04-13 12:48:05 +02:00
nella 4c4c5cf15a Add structural tests for csa_tree. 2026-04-13 12:48:05 +02:00
Emil J 86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef 
Undefine set&reset behavior of $dffsr
 2026-04-08 14:22:34 +00:00
Emil J cede13a742
Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port 
muxpack: fix wide Y port handling
 2026-03-31 10:49:39 +00:00
Gus Smith 6a5fea1b27 Regression test for #5765 2026-03-30 08:59:28 -07:00
Miodrag Milanovic 417e871b06 Fix tests due to ABC improvements 2026-03-30 15:23:27 +01:00
Miodrag Milanović cc915b4c76
Merge pull request #5717 from zaun/latch-support 
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
 2026-03-23 16:51:30 +00:00
Emil J 7b2ab9b245
Merge pull request #5763 from YosysHQ/emil/c-slow-init 
genrtlil: fast memory initialization
 2026-03-23 10:21:21 +00:00
Emil J. Tywoniak 12b443e71c dfflibmap: consistent clk2fflogic usage in test 2026-03-19 19:48:25 +01:00
Emil J 9746bd3897
Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection 
setundef: respect selection for cells, processes, and connections
 2026-03-18 22:53:06 +00:00
Emil J. Tywoniak 27737c6e2e rtlil: add remove2 unit test 2026-03-18 23:33:35 +01:00
Lofty c4cc53a72e synth: fix after abc -fast removal 2026-03-18 17:59:58 +01:00
Emil J c8f715fed8
Merge pull request #5664 from rocallahan/parallel-opt-clean 
Parallelize `opt_clean` pass
 2026-03-16 09:52:34 +00:00
abhinavputhran 314d01b35f changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change 2026-03-08 20:14:03 -04:00
abhinavputhran 47c2257f82 setundef: more tests! and wire selection in -init mode 2026-03-08 19:41:31 -04:00
abhinavputhran c23ba3f917 I think CI runs within the tests directory based on error so I changed the file path 2026-03-08 18:15:35 -04:00
abhinavputhran 5048dac854 setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer 2026-03-06 18:12:03 -05:00
Lofty 050483a6b2
Merge pull request #5698 from YosysHQ/lofty/analogdevices 
synth_analogdevices: synthesis for Analog Devices EFLX FPGAs [sc-273]
 2026-03-06 08:57:59 +00:00
Miodrag Milanovic 602f3fd1a5 Add missing EOL 2026-03-06 09:10:55 +01:00
Miodrag Milanovic 52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Robert O'Callahan 1260fda83a Add 'init' attributes to RTLIL fuzzing 2026-03-06 02:20:08 +00:00
Robert O'Callahan cdfc586f18 Add unit tests for `ConcurrentWorkQueue` 2026-03-06 02:20:08 +00:00
Robert O'Callahan 1e96328ede Add some tests for `ShardedHashSet` 2026-03-06 02:20:08 +00:00
Robert O'Callahan 3910d569da Add unit tests for `ConcurrentQueue` and `ThreadPool` 2026-03-06 02:20:08 +00:00
Robert O'Callahan ac55935a68 Add unit-tests for `ParallelDispatchThread` and friends 2026-03-06 02:20:08 +00:00
Robert O'Callahan 7f3b11e56b Add test that connects a wire with `init` to a constant 2026-03-06 02:20:08 +00:00
Justin Zaun 9288889e20 gowin: add hardware latch support (DL/DLN/DLC/DLP variants) 
Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
 2026-03-05 16:04:23 +01:00
Emil J 629bf3dffd
Merge pull request #5630 from apullin/array-assignment 
ast: Add support for array-to-array assignment
 2026-03-05 11:10:12 +00:00
Lofty cd60dd4912 synth_analogdevices: update timing model and tests 2026-03-05 05:37:13 +00:00
Krystine Sherwin 5d3ed5a418 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-03-05 05:37:13 +00:00
Lofty 39cb61615f analogdevices: DSP inference 2026-03-05 05:37:12 +00:00
Krystine Sherwin 9be3cfb3f9 analogdevices: Update lutram.ys test 2026-03-05 05:37:12 +00:00
Lofty 6f205b41f5 test suite 2026-03-05 05:37:12 +00:00
Andrew Pullin 6ac8c8cb05 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-03-04 21:34:40 -08:00
Emil J 0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
nella b8ee0803ab Remove todo. 2026-03-04 12:39:45 +01:00