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clockgate: test $sdffe rejected

This commit is contained in:
Emil J. Tywoniak 2026-05-07 16:13:14 +02:00
parent 687e5442f2
commit 425d47ad2c
1 changed files with 4 additions and 0 deletions
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4
tests/techmap/clockgate.tcl
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@ -1,5 +1,6 @@
yosys -import
read_verilog clockgate.v
read_verilog ../sim/sdffe.v
yosys proc
opt
@ -194,6 +195,9 @@ select -module dffe_11 -assert-count 0 t:\\neg_small_tielo
select -module dffe_10 -assert-count 1 t:\$_NOT_
select -module dffe_11 -assert-count 0 t:\$_NOT_
# $sdffe is not gated
select -module sdffe -assert-count 0 sdffe t:* t:\$sdffe %d
#------------------------------------------------------------------------------
design -load before