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2633 Commits

Author SHA1 Message Date
nella a800a5b5cb Fix. 2026-06-24 12:13:55 +02:00
nella a8b4715298 Fix. 2026-06-24 11:48:20 +02:00
nella 1186e5af61 Fix. 2026-06-24 11:11:19 +02:00
nella a3b8609c84 Add -nolatches check option. 2026-06-24 10:38:10 +02:00
Miodrag Milanovic a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic 48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Miodrag Milanovic 3ac58b3ac1 Fixed line endings 2026-06-23 07:17:22 +02:00
Miodrag Milanovic 1f0ac8fffc Remove utf-8 marker 2026-06-23 07:14:20 +02:00
Miodrag Milanovic f362e1db0e Remove executable flag from .v files 2026-06-23 07:12:43 +02:00
KrystalDelusion e20a9168fb
Merge pull request #5971 from YosysHQ/krys/upto_indexing 
write_verilog: Fix upto indexing for single bit
 2026-06-22 23:04:16 +00:00
nella 57ec784983
Merge pull request #5953 from YosysHQ/nella/muxcover-enhancements 
Add muxcover x peepopt regression test (#964).
 2026-06-22 10:13:43 +00:00
nella 8f5d2d5894 Use -assert-none. 2026-06-22 11:12:00 +02:00
nella 3d0c868af0
Merge pull request #5952 from YosysHQ/nella/vector-index 
Optimize upto vector indexing (Fix #892).
 2026-06-22 09:05:26 +00:00
nella 6ffc938a75
Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup 
Add warnings and errors to `sim -r` with VCD code path
 2026-06-22 09:02:32 +00:00
Lofty 091d2a7814 Move rename logic to abc_ops_reintegrate 2026-06-19 10:46:47 +01:00
Krystine Sherwin b77bb851ed
tests: Add mixed_upto write_verilog test 2026-06-19 11:20:01 +12:00
nella 5d7486115a
Merge pull request #5887 from YosysHQ/nella/fix-signedness-4402 
Fix: `read_verilog` doesn't respect `signed` keyword
 2026-06-18 16:53:37 +00:00
nella 2195277b5a
Merge pull request #5960 from YosysHQ/nella/latch-infer 
proc_dlatch - infer $adlatch (Fix #5910).
 2026-06-18 16:50:48 +00:00
nella c99a037c33
Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745 
Fix  `chparam` values are unsigned when using read_verilog frontend
 2026-06-18 16:50:22 +00:00
nella b3b1394cf1 Fixup level policy. 2026-06-18 18:00:51 +02:00
nella 32a268d745 Emit errors before dfflegalize. 2026-06-18 17:07:24 +02:00
nella b2d688dbf9 Error out on latches. 2026-06-17 17:36:32 +02:00
nella c814ef35e3 Emit latch warning. 2026-06-17 11:27:43 +02:00
Miodrag Milanović e2903c4a5c
Merge pull request #5959 from YosysHQ/improve_test 
Improve test
 2026-06-16 08:46:11 +00:00
Emil J. Tywoniak 709149c42a opt_muxtree: add reconvergence test 2026-06-15 18:53:44 +02:00
nella c0709b1b4e Fixup issue test. 2026-06-15 16:23:44 +02:00
nella eb4703808a Add tests. 2026-06-15 15:46:13 +02:00
nella a46bc77eeb Fix nolatch test. 2026-06-15 15:27:58 +02:00
Miodrag Milanovic 247bcfed65 Remove old Makefile and fix documentation 2026-06-15 15:25:58 +02:00
nella 01e2698247 Add latch check step. 2026-06-15 15:09:23 +02:00
Emil J. Tywoniak 48c1e1a724 tests: remove hana test with multiple drivers 2026-06-15 15:08:26 +02:00
Miodrag Milanovic 2bab5d3fa5 Add VERBOSE (and V) option to Makefiles 2026-06-15 14:48:11 +02:00
nella 7473fcf939 Add latch inference msg severity option. 2026-06-15 14:17:02 +02:00
nella 309b7d2496 Verify kogge stone impl. 2026-06-12 14:55:47 +02:00
nella c44d24d9fd Add missing -assert to equiv_opt calls. 2026-06-11 01:08:36 +02:00
nella 83a8245734 Add muxcover regression test. 2026-06-10 14:46:04 +02:00
nella 601cd7ba5f Add tests. 2026-06-10 11:30:03 +02:00
nella d52670e58b Replace suitable (2^k-1)-x with ~x. 2026-06-10 11:29:55 +02:00
nella 666bd53f06 Cleanup tests. 2026-06-08 13:47:56 +02:00
nella 3c6900a570 Depth-schedule finar adder. 2026-06-08 13:47:56 +02:00
nella f8d2252735 Use ripple as default final adder, gate fma. 2026-06-08 13:47:56 +02:00
nella d40431f249 Remove black boxes for now. 2026-06-08 13:29:05 +02:00
nella 5e4e5a1d40 Arith tree - parallel prefix. 2026-06-08 13:29:05 +02:00
nella 25eb394ad0 Collapse signed*signed or combined nodes via BW. 2026-06-08 13:29:05 +02:00
nella 6c13ec0efb Test. 2026-06-08 13:29:05 +02:00
Miodrag Milanović 693d5a7eb0
Merge pull request #5903 from YosysHQ/krys/verific_memsize 
verific: Fix non-contiguous memory flattening producing out of bounds accesses in some cases
 2026-06-04 05:43:04 +00:00
Miodrag Milanovic ce280354cf Update CI scripts for CMake 
Co-authored-by: Catherine <whitequark@whitequark.org>
 2026-06-03 08:58:11 +00:00
Catherine a727e7f6e7 Migrate build system to CMake 
See #5895 for details.

This commit does not include CI or documentation changes.
 2026-06-03 08:58:10 +00:00
Catherine bcc736ed7d Revert "Putting back some Makefile.conf" 
This reverts commit d8587f44f0.
 2026-06-02 15:01:50 +00:00
Philippe Sauter c89cfe1e6e peepopt: add shiftpow2 pattern 
Rewrite power-of-two indexed word selects to $bmux when the shift
amount already carries the scale as low zero bits.

Keep the rule to non-overlapping selections and bound the generated
mux ways. Add regressions for aligned shifts, padding, signed
extension, and shiftmul handoff cases.
 2026-05-31 02:01:32 +02:00
Krystine Sherwin 0360a4bd0a
tests/check_mem: Drop unused init check 
It was also raising an error in `read_verilog`.
 2026-05-30 11:06:11 +12:00
Emil J. Tywoniak 80bdbaa010 genrtlil: don't avoid emitting flops for nosync 2026-05-29 11:37:08 +02:00
Krystine Sherwin 52e0030cc5
tests/check_mem: Add problematic case 
Verific reports it as 16 2-bit addresses, meaning we have to iterate over the last dimension while skipping indices.
 2026-05-29 18:40:25 +12:00
Krystine Sherwin ab5f25db9a
Add test for non-contiguous memory init 
Also negative memory addresses.
 2026-05-29 18:40:24 +12:00
Krystine Sherwin aac7366862
tests: Add check_mem to vanilla-test 2026-05-29 18:40:24 +12:00
Krystine Sherwin f6327cc444
check_mem: Add -non-const option 
Can identify potentially dangerous addressing, but also prone to false-positives.
 2026-05-29 18:40:24 +12:00
Krystine Sherwin 07e3d648aa
Add check_mem command 
Comes with a set of tests which (currently) pass with `read_verilog` but fail with `verific` based on #5878.
Add `--check-sv`, an alternative to `--prove-sv` with generator defined yosys commands.  Helpful for when you want to run the same set of commands on a bunch of sv files.
 2026-05-29 18:40:23 +12:00
Miodrag Milanović 1801abf30a
Merge pull request #5913 from YosysHQ/abcexternal 
Putting back some Makefile.conf
 2026-05-28 09:49:16 +00:00
Miodrag Milanovic d8587f44f0 Putting back some Makefile.conf 2026-05-28 11:13:29 +02:00
nella d6106f141c Add matching for fused mac operations for Nexus (fix #5906). 2026-05-28 09:58:18 +02:00
junyao 6f111118de proc: ignore nosync temporaries in always_latch checks 2026-05-26 00:56:07 +08:00
nella 68df0be7d2 Remove eqbits flag. 2026-05-25 14:16:55 +02:00
nella 04a1611346 Tests. 2026-05-20 16:44:52 +02:00
nella d85e3f10de Add tests. 2026-05-20 16:44:52 +02:00
Miodrag Milanovic 4c8e61a52b Expose SBY binary location 2026-05-19 16:08:21 +02:00
Miodrag Milanovic 07924a3c62 Use common.mk for sva tests as well 2026-05-19 15:15:41 +02:00
Miodrag Milanovic 2b3f4c37f5 Fix functional tests 2026-05-19 14:42:08 +02:00
Miodrag Milanovic 15e09163cd Do not use Makefile.conf 2026-05-19 14:29:06 +02:00
Miodrag Milanovic c0779f488a Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
nella 886d0a7043
Merge branch 'main' into gus/sim-with-vcd-tuneup 2026-05-19 12:17:29 +02:00
Emil J. Tywoniak 1c831aa50d threading: whitespace 2026-05-18 16:26:14 +02:00
Miodrag Milanovic 4a4c3a3be6 Make better validation 2026-05-18 08:50:38 +02:00
Miodrag Milanovic ef092e1f15 Include conf so individual test running works 2026-05-18 08:50:20 +02:00
Leon White 59c1bc35cb Fix aiger tests when ABCEXTERNAL is set 2026-05-16 09:12:20 +02:00
nella 38c2806636 Make sure to apply correct signedness to loop vars. 2026-05-13 16:52:07 +02:00
nella 7d3e56523b Preserve param signedness across overrides. 2026-05-13 16:25:15 +02:00
Miodrag Milanovic 1ef6311e5b Update documentation and few more defines 2026-05-13 11:24:45 +02:00
Miodrag Milanovic 7fe32137bd Revert "Fix tests due to ABC improvements" 
This reverts commit 417e871b06.
 2026-05-11 14:47:08 +02:00
Emil J 1f02343268
Merge pull request #5817 from YosysHQ/emil/clockgate-reject-sdffe 
clockgate: reject $sdffe to fix priority handling
 2026-05-08 18:38:51 +00:00
Emil J. Tywoniak 425d47ad2c clockgate: test $sdffe rejected 2026-05-07 16:13:14 +02:00
Emil J. Tywoniak 687e5442f2 clockgate: formal liberty tests 2026-05-07 16:08:55 +02:00
Emil J 4e35ed5955
Merge pull request #5827 from cdleary/cdleary/2026-04-21-sv-positional-assignment-unpacked 
Support positional assignment patterns for unpacked arrays
 2026-05-07 10:55:17 +00:00
Lofty ab316c14d2
Merge pull request #5844 from YosysHQ/lofty/abc-refactor-5 
abc_new: integration testing via synth_gatemate
 2026-05-06 13:40:15 +00:00
Lofty fecea911ff synth_gatemate: add -abc_new option 2026-05-06 14:02:48 +01:00
Lofty 0d3923d086 abc_new: use default script if not specified 2026-04-28 12:33:21 +01:00
Emil J a966d06524
Merge pull request #5825 from petterreinholdtsen/autotest-race-text-busy 
Added locking around compiling in autotest.sh to avoid text busy race.
 2026-04-28 09:12:33 +00:00
Emil J cfa66f5335
Merge pull request #5824 from petterreinholdtsen/autotest-cxxflags 
Use CPPFLAGS and CXXFLAGS when compiling in autotest.sh.
 2026-04-27 22:06:07 +00:00
Petter Reinholdtsen 3187275184 Use CPPFLAGS and CXXFLAGS when compiling in autotest.sh. 
This ensure the build flags used elsewhere are included
also during testing.

Patch based on change from Daniel Gröber via Debian.

See also issue #5805.
 2026-04-25 06:47:26 +02:00
Petter Reinholdtsen 59b3b6d4e4 Added locking around compiling in autotest.sh to avoid text busy race. 
Patch by Daniel Gröber via Debian.

See also issue #5805.
 2026-04-25 00:01:34 +02:00
Petter Reinholdtsen c5a8c3cca5 Made autotest.sh print log on error for easier debugging in CI setups. 
Patch by Daniel Gröber via Debian.

See also issue #5805.
 2026-04-25 00:01:03 +02:00
Emil J ec0a102302
Merge pull request #5832 from YosysHQ/emil/simple-extract 
rtlil: rewrite SigSpec::extract for perf and packing
 2026-04-24 19:03:53 +00:00
Emil J. Tywoniak 10bbda93f7 rtlil: extend SigSpec::extract test 2026-04-24 11:04:19 +02:00
Emil J. Tywoniak a2dafce910 unit tests: rename SigSpec::extract test 2026-04-24 11:04:19 +02:00
Emil J. Tywoniak 25b9b796c4 rtlil: complicate extract again for packing 2026-04-24 11:04:19 +02:00
Christopher D. Leary 390f09b89a Support positional assignment patterns for unpacked arrays 2026-04-23 14:29:38 -07:00
Emil J 2dc69a7578
Merge pull request #5828 from YosysHQ/emil/bash-no-fhs 
Remove FHS dependency by replacing /bin/bash with /usr/bin/env bash
 2026-04-23 15:47:57 +00:00
Emil J. Tywoniak 14d0138d0c Remove FHS dependency by replacing /bin/sh with /usr/bin/env sh 2026-04-23 15:55:11 +02:00
Emil J 64e7ce2f57
Merge pull request #5803 from YosysHQ/emil/specrule-port-sanity 
Fix $specrule port naming inconsistency
 2026-04-22 10:46:36 +00:00
Emil J. Tywoniak f213a34427 Remove FHS dependency by replacing /bin/bash with /usr/bin/env bash everywhere 2026-04-22 10:39:19 +02:00
Miodrag Milanovic a666712687 Update arith_tree tests 2026-04-16 11:04:14 +02:00